Lines Matching refs:FP_TO_SINT
174 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
179 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addTypeForNEON()
301 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in addMVEVectorTypes()
911 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); in ARMTargetLowering()
912 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Custom); in ARMTargetLowering()
965 setTargetDAGCombine(ISD::FP_TO_SINT); in ARMTargetLowering()
1039 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); in ARMTargetLowering()
1041 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom); in ARMTargetLowering()
5785 if (Op.getOpcode() == ISD::FP_TO_SINT || in LowerFP_TO_INT()
5805 DAG.getNode(Op.getOpcode() == ISD::STRICT_FP_TO_SINT ? ISD::FP_TO_SINT in LowerFP_TO_INT()
9362 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X); in LowerSDIV_v4i8()
9401 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerSDIV_v4i16()
9514 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0); in LowerUDIV()
10141 case ISD::FP_TO_SINT: in LowerOperation()
15896 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; in PerformVCVTCombine()
17691 case ISD::FP_TO_SINT: in PerformDAGCombine()