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Searched refs:EXTRACT_VECTOR_ELT (Results 1 – 25 of 40) sorted by relevance

12

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp181 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom); in R600TargetLowering()
182 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f32, Custom); in R600TargetLowering()
183 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); in R600TargetLowering()
184 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); in R600TargetLowering()
251 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in R600TargetLowering()
452 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
698 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
1654 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1663 if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in ReorganizeVector()
1739 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
[all …]
H A DSIISelLowering.cpp280 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
618 case ISD::EXTRACT_VECTOR_ELT: in SITargetLowering()
862 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SITargetLowering()
4575 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
4854 case ISD::EXTRACT_VECTOR_ELT: { in ReplaceNodeResults()
9585 case ISD::EXTRACT_VECTOR_ELT: in isCanonicalized()
10588 if (Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
10589 Op2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
10606 if (FMAOp1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performFMACombine()
10607 FMAOp2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in performFMACombine()
[all …]
H A DAMDGPUISelLowering.cpp1517 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in split64BitValue()
1518 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in split64BitValue()
1528 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in getLoHalf64()
1536 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in getHiHalf64()
1568 HiVT.isVector() ? ISD::EXTRACT_SUBVECTOR : ISD::EXTRACT_VECTOR_ELT, DL, in splitVector()
2220 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, VecSrc, One); in LowerFTRUNC()
2405 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, Zero); in LowerCTLZ_CTTZ()
2406 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Vec, One); in LowerCTLZ_CTTZ()
2546 SDValue Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
2548 SDValue Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, BC, in LowerINT_TO_FP64()
[all …]
H A DAMDGPUISelDAGToDAG.cpp324 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in isExtractHiElt()
352 if (In.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in stripExtractLoElt()
997 if (BaseLo.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
998 BaseHi.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in getBaseWithOffsetUsingSplitOR()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp316 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in ScalarizeVecRes_EXTRACT_SUBVECTOR()
331 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_FP_ROUND()
389 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Op, in ScalarizeVecRes_UnaryOp()
414 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, OpEltVT, Op, in ScalarizeVecRes_VecInregOp()
451 Cond = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, Cond, in ScalarizeVecRes_VSELECT()
569 LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, LHS, in ScalarizeVecRes_SETCC()
571 RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, RHS, in ScalarizeVecRes_SETCC()
626 case ISD::EXTRACT_VECTOR_ELT: in ScalarizeVectorOperand()
3999 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, in WidenVecRes_EXTRACT_SUBVECTOR()
4787 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, in WidenVecOp_BITCAST()
[all …]
H A DLegalizeTypesGeneric.cpp125 Vals.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ElemVT, in ExpandRes_BITCAST()
239 Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
243 Hi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeVectorOps.cpp1492 Oper = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in UnrollStrictFPOp()
1531 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, in UnrollVSETCC()
1533 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, in UnrollVSETCC()
H A DLegalizeFloatTypes.cpp68 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
250 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftenFloatRes_EXTRACT_VECTOR_ELT()
1190 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
2226 case ISD::EXTRACT_VECTOR_ELT: in PromoteFloatResult()
2380 SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT, in PromoteFloatRes_EXTRACT_VECTOR_ELT()
2588 case ISD::EXTRACT_VECTOR_ELT: in SoftPromoteHalfResult()
2670 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), in SoftPromoteHalfRes_EXTRACT_VECTOR_ELT()
H A DLegalizeDAG.cpp1005 case ISD::EXTRACT_VECTOR_ELT: in LegalizeOp()
2959 case ISD::EXTRACT_VECTOR_ELT: in ExpandNode()
3045 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0, in ExpandNode()
3049 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1, in ExpandNode()
3740 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
3743 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), in ExpandNode()
4367 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT || in PromoteNode()
4782 case ISD::EXTRACT_VECTOR_ELT: { in PromoteNode()
4817 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
4866 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT, in PromoteNode()
H A DLegalizeIntegerTypes.cpp70 case ISD::EXTRACT_VECTOR_ELT: in PromoteIntegerResult()
581 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, In, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
586 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, Op0, Op1); in PromoteIntRes_EXTRACT_VECTOR_ELT()
1496 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break; in PromoteIntegerOperand()
2100 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandIntegerResult()
4745 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntRes_EXTRACT_SUBVECTOR()
4898 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Op, in PromoteIntRes_CONCAT_VECTORS()
4971 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in PromoteIntOp_EXTRACT_VECTOR_ELT()
5022 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy, Incoming, in PromoteIntOp_CONCAT_VECTORS()
H A DDAGCombiner.cpp656 case ISD::EXTRACT_VECTOR_ELT: in getStoreSource()
5734 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitAND()
12248 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitTRUNCATE()
12267 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, TrTy, in visitTRUNCATE()
16985 (Val.getOpcode() == ISD::EXTRACT_VECTOR_ELT || in mergeStoresOfConstantsOrVecElts()
18366 InsertVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineInsertEltToShuffle()
18501 if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in visitINSERT_VECTOR_ELT()
18992 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, in visitEXTRACT_VECTOR_ELT()
19459 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in reduceBuildVecToShuffle()
19737 if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) && in visitBUILD_VECTOR()
[all …]
H A DSelectionDAG.cpp3401 case ISD::EXTRACT_VECTOR_ELT: { in computeKnownBits()
4064 case ISD::EXTRACT_VECTOR_ELT: { in ComputeNumSignBits()
4421 case ISD::EXTRACT_VECTOR_ELT: { in isKnownNeverNaN()
4517 if (Ops[i].getOpcode() != ISD::EXTRACT_VECTOR_ELT || in FoldBUILD_VECTOR()
5030 if (OpOpcode == ISD::EXTRACT_VECTOR_ELT && in getNode()
5797 case ISD::EXTRACT_VECTOR_ELT: in getNode()
5821 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in getNode()
5876 return getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, N1.getOperand(0), in getNode()
9892 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT || in matchBinOpReduction()
10030 Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, in UnrollVectorOp()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h511 EXTRACT_VECTOR_ELT, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp202 for (auto Op : {ISD::EXTRACT_VECTOR_ELT, ISD::INSERT_VECTOR_ELT}) in WebAssemblyTargetLowering()
1302 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
1746 if (Op.getOperand(0).getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerSIGN_EXTEND_INREG()
1771 ISD::EXTRACT_VECTOR_ELT, DL, Extract.getValueType(), in LowerSIGN_EXTEND_INREG()
1806 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1813 if (Index->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
1829 if (Lane->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
252 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addMVEVectorTypes()
985 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in ARMTargetLowering()
8506 ISD::EXTRACT_VECTOR_ELT, dl, SVT, in LowerVECTOR_SHUFFLEUsingOneOff()
14444 if (N0->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformVMOVrhCombine()
14724 if (Ext.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in PerformExtractEltToVMOVRRD()
14741 return V->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in PerformExtractEltToVMOVRRD()
14761 ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, in PerformExtractEltToVMOVRRD()
16713 N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in PerformExtendCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp373 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f16, Custom); in NVPTXTargetLowering()
1883 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp, in LowerCONCAT_VECTORS()
1931 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
1933 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Vector, in LowerEXTRACT_VECTOR_ELT()
2169 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2357 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2359 SDValue E1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f16, Val, in LowerSTOREVector()
2367 SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, in LowerSTOREVector()
2581 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, LoadVT, P, in LowerFormalArguments()
4943 SDValue E0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, SubVector, in ReplaceLoadVector()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp360 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal); in SystemZTargetLowering()
646 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in SystemZTargetLowering()
5001 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in tryBuildVectorShuffle()
5522 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
5849 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op, in combineExtract()
5862 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineTruncateExtract()
6189 Op = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), EltVT, in combineEXTRACT_VECTOR_ELT()
6250 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6258 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_ROUND()
6316 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFP_EXTEND()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2011 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in X86TargetLowering()
8284 if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in LowerBuildVectorv4x32()
8482 case ISD::EXTRACT_VECTOR_ELT: in findEltLoadSrc()
9139 if (Opc != ISD::EXTRACT_VECTOR_ELT) { in buildFromShuffleMostly()
10290 if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTORAsVariablePermute()
21928 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
21929 RHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in lowerAddSubToHorizontalOp()
22199 if (I->getOpcode() != ISD::EXTRACT_VECTOR_ELT) in matchScalarReduction()
22366 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in MatchVectorAllZeroTest()
48386 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT && in combineFMA()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp124 setOperationAction(ISD::EXTRACT_VECTOR_ELT, T, Custom); in initializeHVXLowering()
228 setOperationAction(ISD::EXTRACT_VECTOR_ELT, BoolV, Custom); in initializeHVXLowering()
565 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in buildHvxVectorReg()
1276 if (V.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in LowerHvxConcatVectors()
1278 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NTy, in LowerHvxConcatVectors()
2105 case ISD::EXTRACT_VECTOR_ELT: return LowerHvxExtractElement(Op, DAG); in LowerHvxOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp1056 if (ISD == ISD::EXTRACT_VECTOR_ELT && in getVectorInstrCost()
1104 if (ISD == ISD::EXTRACT_VECTOR_ELT || in getVectorInstrCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp920 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); in AArch64TargetLowering()
1426 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
4823 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
8560 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in ReconstructShuffle()
10114 if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in LowerBUILD_VECTOR()
13600 if (Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { in tryCombineFixedPointConvert()
13834 if (LHS.getOpcode() != ISD::EXTRACT_VECTOR_ELT || in performUADDVCombine()
13857 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, in performUADDVCombine()
16547 if (InsertElt.getOpcode() != ISD::EXTRACT_VECTOR_ELT) in removeRedundantInsertVectorElt()
16691 case ISD::EXTRACT_VECTOR_ELT: in PerformDAGCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalVecVT, Legal); in initVPUActions()
314 setOperationAction(ISD::EXTRACT_VECTOR_ELT, LegalPackedVT, Custom); in initVPUActions()
1720 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
2742 assert(Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unknown opcode!"); in lowerEXTRACT_VECTOR_ELT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp442 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::i64, Custom); in RISCVTargetLowering()
464 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
530 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
596 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
681 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
793 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in RISCVTargetLowering()
2148 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, BVec, in LowerOperation()
2262 case ISD::EXTRACT_VECTOR_ELT: in LowerOperation()
3448 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, Idx); in lowerEXTRACT_VECTOR_ELT()
3470 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vec, in lowerEXTRACT_VECTOR_ELT()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp328 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); in addMSAIntType()
382 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); in addMSAFloatType()
465 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
1784 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
1802 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), in lowerINTRINSIC_WO_CHAIN()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp242 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
245 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
859 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
862 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, in LowerCall_32()
1456 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal); in SparcTargetLowering()

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