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Searched refs:EXTRACT_SUBVECTOR (Results 1 – 23 of 23) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp365 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f16, Custom); in AMDGPUTargetLowering()
366 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i16, Custom); in AMDGPUTargetLowering()
367 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom); in AMDGPUTargetLowering()
368 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom); in AMDGPUTargetLowering()
369 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3f32, Custom); in AMDGPUTargetLowering()
370 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v3i32, Custom); in AMDGPUTargetLowering()
371 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom); in AMDGPUTargetLowering()
372 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4i32, Custom); in AMDGPUTargetLowering()
373 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5f32, Custom); in AMDGPUTargetLowering()
374 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v5i32, Custom); in AMDGPUTargetLowering()
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H A DSIISelLowering.cpp282 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
621 case ISD::EXTRACT_SUBVECTOR: in SITargetLowering()
1689 Val = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, NarrowedVT, Val, in convertArgType()
5607 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE()
5922 Data = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MaskPopVT, in constructRetValue()
6391 auto Subvector = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, WidenedOp, in lowerSBuffer()
7500 auto Extract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, NewOp, in getMemIntrinsicNode()
9586 case ISD::EXTRACT_SUBVECTOR: { in isCanonicalized()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp1264 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); in SplitVecRes_EXTRACT_SUBVECTOR()
1267 ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec, in SplitVecRes_EXTRACT_SUBVECTOR()
2430 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, Hi, in SplitVecOp_EXTRACT_SUBVECTOR()
3422 Op = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Op, in WidenVecRes_StrictFP()
4157 if (N.getOpcode() == ISD::EXTRACT_SUBVECTOR) in isSETCCorConvertedSETCC()
4721 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, Res, in WidenVecOp_Convert()
4764 ISD::EXTRACT_SUBVECTOR, dl, DstVT, Res, in WidenVecOp_FP_TO_XINT_SAT()
4872 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), in WidenVecOp_EXTRACT_SUBVECTOR()
5135 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Select, in WidenVecOp_VSELECT()
5554 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, InOp, in ModifyToType()
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H A DDAGCombiner.cpp657 case ISD::EXTRACT_SUBVECTOR: in getStoreSource()
1716 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); in visit()
12470 if (!LegalTypes && N0.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in visitTRUNCATE()
16986 Val.getOpcode() == ISD::EXTRACT_SUBVECTOR)) { in mergeStoresOfConstantsOrVecElts()
17160 OtherBC.getOpcode() != ISD::EXTRACT_SUBVECTOR) in getStoreMergeCandidates()
19694 In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InVT, In, in convertBuildVecZextToZext()
19873 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in combineConcatVectorOfExtracts()
20133 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) in visitCONCAT_VECTORS()
20510 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NVT, in visitEXTRACT_SUBVECTOR()
20571 ISD::EXTRACT_SUBVECTOR, SDLoc(N), NVT, in visitEXTRACT_SUBVECTOR()
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H A DSelectionDAG.cpp2548 case ISD::EXTRACT_SUBVECTOR: { in isSplatValue()
2896 case ISD::EXTRACT_SUBVECTOR: { in computeKnownBits()
4091 case ISD::EXTRACT_SUBVECTOR: { in ComputeNumSignBits()
4563 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR || in foldCONCAT_VECTORS()
5873 if (N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in getNode()
5901 case ISD::EXTRACT_SUBVECTOR: { in getNode()
9560 while (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) in peekThroughExtractSubvectors()
9929 return getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(Op), SubVT, Op, in matchBinOpReduction()
9984 if (Op0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
9985 Op1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in matchBinOpReduction()
[all …]
H A DSelectionDAGDumper.cpp290 case ISD::EXTRACT_SUBVECTOR: return "extract_subvector"; in getOperationName()
H A DLegalizeIntegerTypes.cpp98 case ISD::EXTRACT_SUBVECTOR: in PromoteIntegerResult()
429 InOp = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, InOp, in PromoteIntRes_BITCAST()
1277 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
1525 case ISD::EXTRACT_SUBVECTOR: Res = PromoteIntOp_EXTRACT_SUBVECTOR(N); break; in PromoteIntegerOperand()
4723 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), ExtVT, Ops); in PromoteIntRes_EXTRACT_SUBVECTOR()
4986 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()
H A DSelectionDAGBuilder.cpp412 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, in getCopyFromPartsVector()
750 DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, IntermediateVT, Val, in getCopyToPartsVector()
3653 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Result, in visitShuffleVector()
3698 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Src, in visitShuffleVector()
7190 setValue(&I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ResultVT, Vec, Index)); in visitIntrinsicCall()
H A DTargetLowering.cpp1075 case ISD::EXTRACT_SUBVECTOR: { in SimplifyDemandedBits()
2628 case ISD::EXTRACT_SUBVECTOR: { in SimplifyDemandedVectorElts()
H A DLegalizeDAG.cpp2968 case ISD::EXTRACT_SUBVECTOR: in ExpandNode()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h549 EXTRACT_SUBVECTOR, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp168 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in WebAssemblyTargetLowering()
2191 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorExtendCombine()
2250 if (N->getOpcode() == ISD::EXTRACT_SUBVECTOR) { in performVectorConvertLowCombine()
2325 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in performVectorConvertLowCombine()
2476 case ISD::EXTRACT_SUBVECTOR: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2014 setTargetDAGCombine(ISD::EXTRACT_SUBVECTOR); in X86TargetLowering()
4913 if (Opcode == ISD::EXTRACT_SUBVECTOR) in isTargetShuffleSplat()
6397 if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR && in IsNOT()
6776 if (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in getTargetConstantBitsFromNode()
8086 if (Opcode == ISD::EXTRACT_SUBVECTOR) { in getShuffleScalarElt()
13624 N0.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
13625 N1.getOpcode() != ISD::EXTRACT_SUBVECTOR || in lowerShuffleOfExtractsAsVperm()
13712 case ISD::EXTRACT_SUBVECTOR: { in lowerShuffleAsBroadcast()
43812 BC0.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineHorizOpWithShuffle()
43813 BC1.getOpcode() == ISD::EXTRACT_SUBVECTOR && in combineHorizOpWithShuffle()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1430 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForNEON()
1490 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addTypeForFixedLengthSVE()
4606 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4610 DAG.getNode(ISD::EXTRACT_SUBVECTOR, Dl, in LowerSTORE()
4831 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
9320 } else if (V.getOpcode() == ISD::EXTRACT_SUBVECTOR) { in constructDup()
13520 if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
13521 N01->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
13522 N10->getOpcode() == ISD::EXTRACT_SUBVECTOR && in performConcatVectorsCombine()
13682 if (N.getOpcode() != ISD::EXTRACT_SUBVECTOR) in isEssentiallyExtractHighSubvector()
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H A DAArch64ISelDAGToDAG.cpp646 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR) in checkHighLaneIndex()
2073 if (Extract.getOpcode() != ISD::EXTRACT_SUBVECTOR) in tryHighFPExt()
3474 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp123 setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom); in initializeHVXLowering()
227 setOperationAction(ISD::EXTRACT_SUBVECTOR, BoolV, Custom); in initializeHVXLowering()
1968 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, RetTy, in WidenHvxSetCC()
2050 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResTy, in WidenHvxTruncate()
2104 case ISD::EXTRACT_SUBVECTOR: return LowerHvxExtractSubvector(Op, DAG); in LowerHvxOperation()
H A DHexagonISelLowering.cpp1651 ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, in HexagonTargetLowering()
1700 setOperationAction(ISD::EXTRACT_SUBVECTOR, NativeVT, Custom); in HexagonTargetLowering()
3178 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp461 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
556 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
623 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
675 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
788 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in RISCVTargetLowering()
1334 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V, Zero); in convertFromScalableVector()
1554 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec, in lowerBUILD_VECTOR()
2501 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
4092 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ExtSubVecVT, Vec, in lowerEXTRACT_SUBVECTOR()
4149 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InterSubVT, Vec, in lowerEXTRACT_SUBVECTOR()
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H A DRISCVISelDAGToDAG.cpp1311 case ISD::EXTRACT_SUBVECTOR: { in Select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp185 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal); in addTypeForNEON()
432 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); in addMVEVectorTypes()
6082 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast, in CombineVMOVDRRCandidateWithVecOp()
9421 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9423 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9425 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerSDIV()
9427 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerSDIV()
9458 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, in LowerUDIV()
9460 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1, in LowerUDIV()
9797 Pred = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MemVT, Pred, in LowerPredicateLoad()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td685 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
690 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2167 case ISD::EXTRACT_SUBVECTOR: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp7800 Op1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
7802 Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, in LowerTRUNCATEVector()
10762 case ISD::EXTRACT_SUBVECTOR: { in LowerFP_EXTEND()