185   setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);  in addTypeForNEON()
432     setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom);  in addMVEVectorTypes()
6082   return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,  in CombineVMOVDRRCandidateWithVecOp()
8018           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,  in ReconstructShuffle()
8024           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,  in ReconstructShuffle()
8029           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,  in ReconstructShuffle()
8032           DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,  in ReconstructShuffle()
9421     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,  in LowerSDIV()
9423     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,  in LowerSDIV()
9425     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,  in LowerSDIV()
9427     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,  in LowerSDIV()
9458     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,  in LowerUDIV()
9460     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,  in LowerUDIV()
9462     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,  in LowerUDIV()
9464     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,  in LowerUDIV()
9797     Pred = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MemVT, Pred,  in LowerPredicateLoad()
10169   case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG, Subtarget);  in LowerOperation()
12959         DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext0.getOperand(0),  in PerformVQDMULHCombine()
12962         DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, LegalVecVT, Ext1.getOperand(0),  in PerformVQDMULHCombine()
15678         DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, NewFromVT, Trunc.getOperand(0),  in PerformSplittingToNarrowingStores()
19984   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()