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Searched refs:Defs (Results 1 – 25 of 179) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrSystem.td25 let hasSideEffects = 1, Defs = [CC] in {
33 let Uses = [R2L], Defs = [R2L] in
135 let hasSideEffects = 1, Defs = [CC] in
139 let hasSideEffects = 1, Defs = [CC] in
195 let hasSideEffects = 1, Defs = [CC] in
220 let hasSideEffects = 1, Defs = [CC] in
256 let hasSideEffects = 1, Defs = [CC] in
268 let hasSideEffects = 1, Defs = [CC] in
278 let hasSideEffects = 1, Defs = [CC] in
290 let Defs = [CC] in
[all …]
H A DSystemZInstrHFP.td21 let Defs = [CC] in {
60 let Defs = [CC] in {
71 let Defs = [CC] in {
77 let Defs = [CC] in {
88 let Defs = [CC] in {
95 let Defs = [CC] in {
102 let Defs = [CC] in {
131 let Defs = [CC] in {
142 let Defs = [CC] in {
152 let Defs = [CC] in {
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H A DSystemZInstrDFP.td22 let Uses = [FPC], Defs = [CC] in {
66 let Uses = [FPC], Defs = [CC] in {
78 let Uses = [FPC], Defs = [CC] in {
116 let Defs = [CC, R1L, F0Q], Uses = [FPC, R0L, F4Q] in
145 let Uses = [FPC], Defs = [CC] in {
157 let Uses = [FPC], Defs = [CC] in {
216 let Uses = [FPC], Defs = [CC] in {
222 let Uses = [FPC], Defs = [CC] in {
228 let Defs = [CC] in {
234 let Defs = [CC] in {
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H A DSystemZInstrInfo.td133 let Defs = [CC] in {
191 let Defs = [CC] in {
206 let Defs = [CC] in {
856 let Defs = [CC] in {
866 let Defs = [CC] in {
876 let Defs = [CC] in {
901 let Defs = [CC] in {
1153 let Defs = [CC] in {
1826 let Defs = [CC];
2046 let Defs = [CC] in
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp100 BitVector Defs, Uses; member
129 void getDefsUses(const MachineInstr *MI, BitVector &Defs,
165 expandReg(*R++, Defs); in getDefsUses()
175 BitVector &Set = MO.isDef() ? Defs : Uses; in getDefsUses()
184 BitVector Defs(NR), Uses(NR); in buildMaps() local
189 Defs.reset(); in buildMaps()
191 getDefsUses(MI, Defs, Uses); in buildMaps()
287 if (!DU.Defs[PR]) in genMuxInBlock()
311 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { in genMuxInBlock()
315 if (CanDown && DU.Defs[SR1]) in genMuxInBlock()
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H A DHexagonPseudo.td85 let Defs = [R29, R30, R31], Uses = [R29], isPseudo = 1 in
91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
182 Defs = [PC, R31, R6, R7, P0] in
312 let Defs = [R29], hasSideEffects = 1 in
359 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
374 let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
389 let Defs = [P0] in
392 let Defs = [P0], isExtended = 1, opExtendable = 0 in
395 let Defs = [R14, R15, R28] in
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFormMemoryClauses.cpp63 bool canBundle(const MachineInstr &MI, const RegUse &Defs,
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
170 const RegUse &Map = MO.isDef() ? Uses : Defs; in canBundle()
230 RegUse &Map = MO.isDef() ? Defs : Uses; in collectRegUses()
247 RegUse &Defs, RegUse &Uses, in processRegUses() argument
249 if (!canBundle(MI, Defs, Uses)) in processRegUses()
255 collectRegUses(MI, Defs, Uses); in processRegUses()
303 RegUse Defs, Uses; in runOnMachineFunction() local
304 if (!processRegUses(MI, Defs, Uses, RPT)) { in runOnMachineFunction()
322 if (!processRegUses(*Next, Defs, Uses, RPT)) in runOnMachineFunction()
[all …]
H A DSIPostRABundler.cpp49 SmallSet<Register, 16> Defs; member in __anon8aedb7080111::SIPostRABundler
83 for (Register Def : Defs) in isDependentLoad()
140 assert(Defs.empty()); in runOnMachineFunction()
143 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
155 Defs.insert(I->defs().begin()->getReg()); in runOnMachineFunction()
208 Defs.clear(); in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp68 RegisterSet &Defs, RegisterSet &Uses);
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses, in INITIALIZE_PASS()
106 InsertUsesDefs(LocalDefs, Defs); in INITIALIZE_PASS()
138 RegisterSet &Defs, RegisterSet &Uses) { in MoveCopyOutOfITBlock() argument
152 if (Uses.count(DstReg) || Defs.count(SrcReg)) in MoveCopyOutOfITBlock()
196 RegisterSet Defs, Uses; in InsertITInstructions() local
209 Defs.clear(); in InsertITInstructions()
211 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
252 MoveCopyOutOfITBlock(NMI, CC, OCC, Defs, Uses)) { in InsertITInstructions()
262 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td98 class Defs<list<Register> Regs> {
99 list<Register> Defs = Regs;
561 Defs<[DSPOutFlag20]>;
569 Defs<[DSPOutFlag20]>;
577 Defs<[DSPOutFlag20]>;
585 Defs<[DSPOutFlag20]>;
601 Defs<[DSPCarry]>;
852 Defs<[DSPCCond]>;
856 Defs<[DSPCCond]>;
908 Defs<[DSPOutFlag23]>;
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H A DMipsDelaySlotFiller.cpp136 BitVector Defs, Uses; member in __anon7ffcee0a0111::RegDefsUses
202 SmallPtrSet<ValueType, 4> Uses, Defs; member in __anon7ffcee0a0111::MemDefsUses
354 Defs.set(Mips::RA); in init()
360 Defs.reset(Mips::AT); in init()
371 Defs.set(Mips::RA); in setCallerSaved()
372 Defs.set(Mips::RA_64); in setCallerSaved()
386 Defs |= CallerSavedRegs; in setCallerSaved()
399 Defs |= AllocSet.flip(); in setUnallocatableRegs()
428 Defs |= NewDefs; in update()
444 return isRegInSet(Defs, Reg); in checkRegDefsUses()
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H A DMicroMipsDSPInstrInfo.td227 Defs<[DSPOutFlag22]>;
230 Defs<[DSPOutFlag22]>;
233 Defs<[DSPOutFlag22]>;
236 Defs<[DSPOutFlag22]>;
264 Defs<[DSPOutFlag22]>;
313 Defs<[DSPOutFlag23]>;
316 Defs<[DSPOutFlag23]>;
319 Defs<[DSPOutFlag23]>;
322 Defs<[DSPOutFlag23]>;
325 Defs<[DSPOutFlag23]>;
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBoolRetToInt.cpp73 SmallPtrSet<Value *, 8> Defs; in findAllDefs() local
76 Defs.insert(V); in findAllDefs()
84 if (Defs.insert(Op).second) in findAllDefs()
87 return Defs; in findAllDefs()
222 auto Defs = findAllDefs(U); in runOnUse() local
225 if (llvm::none_of(Defs, [](Value *V) { return isa<Instruction>(V); })) in runOnUse()
231 for (Value *V : Defs) in runOnUse()
236 for (Value *V : Defs) in runOnUse()
247 for (Value *V : Defs) in runOnUse()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp486 while (!Defs.empty()) { in UpdatePhysRegDefs()
487 Register Reg = Defs.back(); in UpdatePhysRegDefs()
488 Defs.pop_back(); in UpdatePhysRegDefs()
557 HandlePhysRegDef(MOReg, &MI, Defs); in runOnInstr()
559 UpdatePhysRegDefs(MI, Defs); in runOnInstr()
564 SmallVector<unsigned, 4> Defs; in runOnBlock() local
579 runOnInstr(MI, Defs); in runOnBlock()
612 HandlePhysRegDef(i, nullptr, Defs); in runOnBlock()
762 DenseSet<unsigned> Defs, Kills; in addNewBlock() local
780 Defs.insert(Op.getReg()); in addNewBlock()
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H A DReachingDefAnalysis.cpp397 InstSet &Defs) const { in getGlobalReachingDefs()
399 Defs.insert(Def); in getGlobalReachingDefs()
404 getLiveOuts(MBB, PhysReg, Defs); in getGlobalReachingDefs()
408 MCRegister PhysReg, InstSet &Defs) const { in getLiveOuts()
410 getLiveOuts(MBB, PhysReg, Defs, VisitedBBs); in getLiveOuts()
414 MCRegister PhysReg, InstSet &Defs, in getLiveOuts() argument
426 Defs.insert(Def); in getLiveOuts()
429 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); in getLiveOuts()
556 SmallSet<int, 2> Defs; in isSafeToMove() local
562 Defs.insert(MO.getReg()); in isSafeToMove()
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/freebsd-13.1/contrib/llvm-project/clang/utils/TableGen/
H A DNeonEmitter.cpp2001 for (auto *Def : Defs) { in genBuiltinsDef()
2035 for (auto *Def : Defs) { in genOverloadTypeCheckCode()
2105 for (auto *Def : Defs) { in genIntrinsicRangeCheckCode()
2192 createIntrinsic(R, Defs); in runHeader()
2195 genBuiltinsDef(OS, Defs); in runHeader()
2370 for (auto *I : Defs) in run()
2408 I = Defs.erase(I); in run()
2479 for (auto *I : Defs) in runFP16()
2517 I = Defs.erase(I); in runFP16()
2556 for (auto *I : Defs) in runBF16()
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H A DRISCVVEmitter.cpp918 std::vector<std::unique_ptr<RVVIntrinsic>> Defs; in createHeader() local
919 createRVVIntrinsics(Defs); in createHeader()
974 std::stable_sort(Defs.begin(), Defs.end(), in createHeader()
1006 createRVVIntrinsics(Defs); in createBuiltins()
1012 for (auto &Def : Defs) { in createBuiltins()
1025 createRVVIntrinsics(Defs); in createCodeGen()
1027 std::stable_sort(Defs.begin(), Defs.end(), in createCodeGen()
1034 RVVIntrinsic *PrevDef = Defs.begin()->get(); in createCodeGen()
1035 for (auto &Def : Defs) { in createCodeGen()
1044 Defs.back()->emitCodeGenSwitchBody(OS); in createCodeGen()
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H A DSveEmitter.cpp1230 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createHeader() local
1233 createIntrinsic(R, Defs); in createHeader()
1240 Defs.begin(), Defs.end(), [](const std::unique_ptr<Intrinsic> &A, in createHeader()
1249 for (auto &I : Defs) { in createHeader()
1291 SmallVector<std::unique_ptr<Intrinsic>, 128> Defs; in createBuiltins() local
1293 createIntrinsic(R, Defs); in createBuiltins()
1302 for (auto &Def : Defs) { in createBuiltins()
1324 createIntrinsic(R, Defs); in createCodeGenMap()
1333 for (auto &Def : Defs) { in createCodeGenMap()
1357 createIntrinsic(R, Defs); in createRangeChecks()
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H A DClangDataCollectorsEmitter.cpp8 const auto &Defs = RK.getClasses(); in EmitClangDataCollectors() local
9 for (const auto &Entry : Defs) { in EmitClangDataCollectors()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCChecker.cpp45 Defs[Hexagon::LC0].insert(Unconditional); in init()
49 Defs[Hexagon::LC1].insert(Unconditional); in init()
127 Defs[R].insert(PredSense(PredReg, isTrue)); in init()
182 Defs[*SRI].insert(PredSense(PredReg, isTrue)); in init()
394 if (!Defs.count(P) || LatePreds.count(P) || Defs.count(Hexagon::P3_0)) { in checkPredicates()
407 if (LatePreds.count(P) > 1 || Defs.count(P)) { in checkPredicates()
507 for (unsigned j = 0; j < Defs; ++j) { in checkRegistersReadOnly()
577 for (const auto &I : Defs) { in checkRegisters()
580 if (isLoopRegister(R) && Defs.count(R) > 1 && in checkRegisters()
596 if (!isPredicateRegister(R) && Defs[R].size() > 1) { in checkRegisters()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/
H A DMemorySSAUpdater.cpp158 if (Defs) { in getPreviousDefInBlock()
163 if (Iter != Defs->rend()) in getPreviousDefInBlock()
184 if (Defs) { in getPreviousDefFromEnd()
186 return &*Defs->rbegin(); in getPreviousDefFromEnd()
264 (void)Defs; in insertUse()
265 assert((!Defs || (++Defs->begin() == Defs->end())) && in insertUse()
478 if (++DefIter != Defs->end()) { in fixupDefs()
499 auto *FirstDef = &*Defs->begin(); in fixupDefs()
870 if (Defs) in applyInsertUpdates()
871 return &*(--Defs->end()); in applyInsertUpdates()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrKL.td20 let Uses = [XMM0, EAX], Defs = [EFLAGS] in {
27 let Uses = [XMM0], Defs = [XMM0, XMM1, XMM2, XMM4, XMM5, XMM6, EFLAGS] in {
33 let Uses = [XMM0, XMM1], Defs = [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, EFLAGS] in {
40 Defs = [EFLAGS] in {
70 Defs = [EFLAGS, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7],
H A DX86InstrTSX.td27 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
35 let isPseudo = 1, Defs = [EAX] in {
42 let Defs = [EFLAGS] in
H A DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
91 let Defs = [AL] in
94 let Defs = [AX] in
97 let Defs = [EAX] in
474 let Defs = [SSP] in {
479 } // Defs SSP
496 } // Defs SSP
512 let Defs = [SSP] in {
521 } // Defs SSP
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/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCTagsEmitter.cpp66 const auto &Defs = Records.getDefs(); in run() local
69 Tags.reserve(Classes.size() + Defs.size()); in run()
72 for (const auto &D : Defs) in run()

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