| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ModuloSchedule.h | 89 DenseMap<MachineInstr *, int> Cycle; variable
107 DenseMap<MachineInstr *, int> Cycle, in ModuloSchedule() argument
109 : Loop(Loop), ScheduledInstrs(ScheduledInstrs), Cycle(std::move(Cycle)), in ModuloSchedule()
126 int getFirstCycle() { return Cycle[ScheduledInstrs.front()]; } in getFirstCycle()
130 int getFinalCycle() { return Cycle[ScheduledInstrs.back()]; } in getFinalCycle()
140 auto I = Cycle.find(MI); in getCycle()
141 return I == Cycle.end() ? -1 : I->second; in getCycle()
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| H A D | ScheduleDAG.h | 546 void setCurCycle(unsigned Cycle) { in setCurCycle() argument
547 CurCycle = Cycle; in setCurCycle()
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| H A D | MachineTraceMetrics.h | 77 unsigned Cycle = 0; member
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | P9InstrResources.td | 705 // 6 Cycle Load uses a single slice.
1137 // 33 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1144 // 36 Cycle DP Instruction.
1157 // 36 Cycle DP Vector Instruction.
1164 // 27 Cycle DP Vector Instruction.
1171 // 36 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1178 // 26 Cycle DP Instruction.
1190 // 26 Cycle DP Instruction Restricted and Cracked with 3 Cycle ALU.
1209 // 22 Cycle DP Instruction Restricted and Cracked with 2 Cycle ALU.
1297 // Two Cycle Branch
[all …]
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| H A D | PPCInstrInfo.cpp | 156 int Cycle = ItinData->getOperandCycle(DefClass, i); in getInstrLatency() local
157 if (Cycle < 0) in getInstrLatency()
160 Latency = std::max(Latency, (unsigned) Cycle); in getInstrLatency()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineTraceMetrics.cpp | 792 unsigned Cycle = 0; in updateDepth() local
805 Cycle = std::max(Cycle, DepCycle); in updateDepth()
809 MICycles.Depth = Cycle; in updateDepth()
919 unsigned DepHeight = I->Cycle; in updatePhysDepsUpwards()
939 LRU.Cycle = Height; in updatePhysDepsUpwards()
1038 RegUnits[LI.Reg].Cycle = LI.Height; in computeInstrHeights()
1098 unsigned Cycle = 0; in computeInstrHeights() local
1101 Cycle = HeightI->second; in computeInstrHeights()
1113 Cycle = updatePhysDepsUpwards(MI, Cycle, RegUnits, MTM.SchedModel, in computeInstrHeights()
1122 MICycles.Height = Cycle; in computeInstrHeights()
[all …]
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| H A D | MachinePipeliner.cpp | 614 for (int Cycle = Schedule.getFirstCycle(); Cycle <= Schedule.getFinalCycle(); in schedule() local
615 ++Cycle) { in schedule()
616 for (SUnit *SU : Schedule.getInstructions(Cycle)) { in schedule()
618 Cycles[SU->getInstr()] = Cycle; in schedule()
2914 for (int Cycle = getFirstCycle(), E = getFinalCycle(); Cycle <= E; ++Cycle) { in finalizeSchedule() local
2915 std::deque<SUnit *> &cycleInstrs = ScheduledInstrs[Cycle]; in finalizeSchedule()
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| H A D | ModuloSchedule.cpp | 2139 static void parseSymbolString(StringRef S, int &Cycle, int &Stage) { in parseSymbolString() argument
2153 CycleTokenAndValue.second.drop_front().getAsInteger(10, Cycle); in parseSymbolString()
2155 dbgs() << " Stage=" << Stage << ", Cycle=" << Cycle << "\n"; in parseSymbolString()
2163 DenseMap<MachineInstr *, int> Cycle, Stage; in runOnLoop() local
2171 parseSymbolString(Sym->getName(), Cycle[&MI], Stage[&MI]); in runOnLoop()
2175 ModuloSchedule MS(MF, &L, std::move(Instrs), std::move(Cycle), in runOnLoop()
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| H A D | IfConversion.cpp | 287 unsigned Cycle, unsigned Extra, in MeetIfcvtSizeLimit() argument
289 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra, in MeetIfcvtSizeLimit()
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| /freebsd-13.1/contrib/llvm-project/clang/include/clang/AST/ |
| H A D | ASTImporter.h | 197 using Cycle = llvm::iterator_range<VecTy::const_reverse_iterator>; variable
198 Cycle getCycleAtBack() const { in getCycleAtBack()
200 return Cycle(Nodes.rbegin(), in getCycleAtBack()
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| /freebsd-13.1/sys/contrib/device-tree/Bindings/regulator/ |
| H A D | pwm-regulator.txt | 33 - voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
85 /* Voltage Duty-Cycle */
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonLoopIdiomRecognition.cpp | 1134 ValueSeq &Cycle) { in findCycle() argument
1155 if (Cycle.count(I)) in findCycle()
1157 Cycle.insert(I); in findCycle()
1160 Cycle.remove(I); in findCycle()
1162 return !Cycle.empty(); in findCycle()
1172 unsigned I, N = Cycle.size(); in classifyCycle()
1174 Value *V = Cycle[I]; in classifyCycle()
1186 First.insert(Cycle[J]); in classifyCycle()
1189 Second.insert(Cycle[I]); in classifyCycle()
1191 Value *V = Cycle[I]; in classifyCycle()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 398 bool contains(unsigned Cycle) const { return Cycle >= Begin && Cycle < End; } in contains() argument
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.cpp | 439 unsigned Cycle = getTransSwizzle(TransSwz, i); in isLegalUpTo() local
444 if (Vector[Src.second][Cycle] < 0) in isLegalUpTo()
445 Vector[Src.second][Cycle] = Src.first; in isLegalUpTo()
446 if (Vector[Src.second][Cycle] != Src.first) in isLegalUpTo()
500 unsigned Cycle = getTransSwizzle(TransSwz, i); in isConstCompatible() local
503 if (ConstCount > 0 && Cycle == 0) in isConstCompatible()
505 if (ConstCount > 1 && Cycle == 1) in isConstCompatible()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RegisterFile.h | 62 void notifyExecuted(unsigned Cycle);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 38 void WriteRef::notifyExecuted(unsigned Cycle) { in notifyExecuted() argument
40 WriteBackCycle = Cycle; in notifyExecuted()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedTSV110.td | 37 def TSV110UnitMDU : ProcResource<1>; // Multi-Cycle
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| /freebsd-13.1/contrib/processor-trace/libipt/include/ |
| H A D | intel-pt.h.in | 272 * multi-byte CYC (Cycle Count) packet, instead of any remaining bytes
339 * single CYC (Cycle Count) packet, possibly along with an associated
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ScheduleZnver3.td | 1451 // Zero Cycle Move
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| /freebsd-13.1/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | DiagnosticSemaKinds.td | 3632 "Cycle in acquired_before/after dependencies, starting with '%0'">,
6240 let CategoryName = "ARC Retain Cycle" in {
6249 } // end "ARC Retain Cycle" category
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