| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopBoundSplit.cpp | 58 Cond.ICmp = ICmp; in analyzeICmp()
59 if (match(ICmp, m_ICmp(Cond.Pred, m_Value(Cond.AddRecValue), in analyzeICmp()
61 Cond.AddRecSCEV = SE.getSCEV(Cond.AddRecValue); in analyzeICmp()
62 Cond.BoundSCEV = SE.getSCEV(Cond.BoundValue); in analyzeICmp()
66 std::swap(Cond.AddRecValue, Cond.BoundValue); in analyzeICmp()
67 std::swap(Cond.AddRecSCEV, Cond.BoundSCEV); in analyzeICmp()
68 Cond.Pred = ICmpInst::getSwappedPredicate(Cond.Pred); in analyzeICmp()
85 if (Cond.Pred == ICmpInst::ICMP_SLT || Cond.Pred == ICmpInst::ICMP_ULT) in calculateUpperBound()
91 if (Cond.Pred != ICmpInst::ICMP_ULE && Cond.Pred != ICmpInst::ICMP_SLE) in calculateUpperBound()
213 Cond.BI = ExitingBI; in canSplitLoopBound()
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| H A D | LoopUnswitch.cpp | 439 auto CacheIt = Cache.find(Cond); in findLIVLoopCondition()
447 if (Cond->getType()->isVectorTy()) in findLIVLoopCondition()
457 Cache[Cond] = Cond; in findLIVLoopCondition()
458 return Cond; in findLIVLoopCondition()
497 Cache[Cond] = LHS; in findLIVLoopCondition()
505 Cache[Cond] = RHS; in findLIVLoopCondition()
511 Cache[Cond] = nullptr; in findLIVLoopCondition()
586 Value *Cond = BInst->getCondition(); in isUnreachableDueToPreviousUnswitching() local
587 if (!isa<ConstantInt>(Cond)) in isUnreachableDueToPreviousUnswitching()
591 Cond == ConstantInt::getTrue(Cond->getContext()) in isUnreachableDueToPreviousUnswitching()
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| /freebsd-13.1/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
| H A D | SimpleConstraintManager.cpp | 26 DefinedSVal Cond, in assume() argument
29 if (Optional<Loc> LV = Cond.getAs<Loc>()) { in assume()
41 return assume(State, Cond.castAs<NonLoc>(), Assumption); in assume()
46 State = assumeAux(State, Cond, Assumption); in assume()
48 return EE->processAssume(State, Cond, Assumption); in assume()
53 NonLoc Cond, in assumeAux() argument
58 if (!canReasonAbout(Cond)) { in assumeAux()
60 SymbolRef Sym = Cond.getAsSymbol(); in assumeAux()
65 switch (Cond.getSubKind()) { in assumeAux()
70 nonloc::SymbolVal SV = Cond.castAs<nonloc::SymbolVal>(); in assumeAux()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrInfo.cpp | 126 Cond.push_back(MachineOperand::CreateImm(true)); in analyzeBranch()
127 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
134 Cond.push_back(MachineOperand::CreateImm(false)); in analyzeBranch()
135 Cond.push_back(MI.getOperand(1)); in analyzeBranch()
180 if (Cond.empty()) { in insertBranch()
188 assert(Cond.size() == 2 && "Expected a flag and a successor block"); in insertBranch()
190 if (Cond[0].getImm()) in insertBranch()
191 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]); in insertBranch()
202 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
203 assert(Cond.size() == 2 && "Expected a flag and a condition expression"); in reverseBranchCondition()
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| H A D | WebAssemblyLowerBrUnless.cpp | 71 Register Cond = MI->getOperand(1).getReg(); in runOnMachineFunction() local
75 if (MFI.isVRegStackified(Cond)) { in runOnMachineFunction()
76 assert(MRI.hasOneDef(Cond)); in runOnMachineFunction()
77 MachineInstr *Def = MRI.getVRegDef(Cond); in runOnMachineFunction()
178 Cond = Def->getOperand(1).getReg(); in runOnMachineFunction()
193 .addReg(Cond); in runOnMachineFunction()
195 Cond = Tmp; in runOnMachineFunction()
204 .addReg(Cond); in runOnMachineFunction()
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| H A D | WebAssemblyFixBrTableDefaults.cpp | 97 SmallVector<MachineOperand, 2> Cond; in fixBrTableDefault() local
99 bool Analyzed = !TII.analyzeBranch(*HeaderMBB, TBB, FBB, Cond); in fixBrTableDefault()
114 assert(Cond.size() == 2 && Cond[1].isReg() && "Unexpected condition info"); in fixBrTableDefault()
123 auto *RangeCheck = MRI.getVRegDef(Cond[1].getReg()); in fixBrTableDefault()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 138 Value *Cond = nullptr; in performCallDomainErrorOnly() local
183 shrinkWrapCI(CI, Cond); in performCallDomainErrorOnly()
190 Value *Cond = nullptr; in performCallRangeErrorOnly() local
208 Cond = generateTwoRangeCond(CI, Func); in performCallRangeErrorOnly()
215 Cond = generateOneRangeCond(CI, Func); in performCallRangeErrorOnly()
221 shrinkWrapCI(CI, Cond); in performCallRangeErrorOnly()
228 Value *Cond = nullptr; in performCallErrors() local
275 Cond = generateCondForPow(CI, Func); in performCallErrors()
276 if (Cond == nullptr) in performCallErrors()
284 shrinkWrapCI(CI, Cond); in performCallErrors()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430InstrInfo.cpp | 132 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
133 assert(Cond.size() == 1 && "Invalid Xbranch condition!"); in reverseBranchCondition()
159 Cond[0].setImm(CC); in reverseBranchCondition()
166 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
201 Cond.clear(); in analyzeBranch()
225 if (Cond.empty()) { in analyzeBranch()
228 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
234 assert(Cond.size() == 1); in analyzeBranch()
256 ArrayRef<MachineOperand> Cond, in insertBranch() argument
261 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreInstrInfo.cpp | 220 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
221 Cond.push_back(LastInst->getOperand(0)); in analyzeBranch()
241 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
242 Cond.push_back(SecondLastInst->getOperand(0)); in analyzeBranch()
279 assert((Cond.size() == 2 || Cond.size() == 0) && in insertBranch()
284 if (Cond.empty()) { in insertBranch()
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
297 assert(Cond.size() == 2 && "Unexpected number of components!"); in insertBranch()
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg()) in insertBranch()
404 assert((Cond.size() == 2) && in reverseBranchCondition()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 202 if (!Cond.empty()) in analyzeBranch()
208 Cond.push_back(I->getOperand(1)); in analyzeBranch()
209 Cond.push_back(I->getOperand(2)); in analyzeBranch()
210 Cond.push_back(I->getOperand(3)); in analyzeBranch()
225 Cond.clear(); in analyzeBranch()
351 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
352 assert((Cond.size() == 3) && "Invalid ARC branch condition!"); in reverseBranchCondition()
353 Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm())); in reverseBranchCondition()
379 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
382 if (Cond.empty()) { in insertBranch()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrInfo.cpp | 98 SmallVectorImpl<MachineOperand> &Cond, in analyzeBranch() argument
116 Cond.push_back(LastInst.getOperand(0)); in analyzeBranch()
134 Cond.push_back(SecondLastInst.getOperand(0)); in analyzeBranch()
183 ArrayRef<MachineOperand> Cond, in insertBranch() argument
190 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
195 if (Cond.empty()) // Unconditional branch in insertBranch()
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()) in insertBranch()
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB); in insertBranch()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFAdjustOpt.cpp | 182 auto *Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB() local
183 if (!Cond || B2->getFirstNonPHI() != Cond) in serializeICMPCrossBB()
185 Value *B2Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
186 auto Cond2Op = Cond->getPredicate(); in serializeICMPCrossBB()
192 Cond = dyn_cast<ICmpInst>(BI->getCondition()); in serializeICMPCrossBB()
193 if (!Cond) in serializeICMPCrossBB()
195 Value *B1Op0 = Cond->getOperand(0); in serializeICMPCrossBB()
196 auto Cond1Op = Cond->getPredicate(); in serializeICMPCrossBB()
211 PassThroughInfo Info(Cond, BI, 0); in serializeICMPCrossBB()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 2086 Cond = Cond.getOperand(0); in LowerSELECT()
2158 Cond = Cond.getOperand(0); in LowerSELECT()
2162 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { in LowerSELECT()
2173 Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG); in LowerSELECT()
2260 Cond = Cond.getOperand(0); in LowerBRCOND()
2271 Cond = Cond.getOperand(0); in LowerBRCOND()
2293 Cond = Cond.getNode()->getOperand(1); in LowerBRCOND()
2407 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { in LowerBRCOND()
2415 Cond = Cond.getOperand(0).getOperand(1); in LowerBRCOND()
2423 Cond = Cond.getOperand(0); in LowerBRCOND()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 92 Cond.push_back(Inst->getOperand(i)); in AnalyzeCondBr()
109 unsigned Opc = Cond[0].getImm(); in BuildCondBr()
113 for (unsigned i = 1; i < Cond.size(); ++i) { in BuildCondBr()
114 assert((Cond[i].isImm() || Cond[i].isReg()) && in BuildCondBr()
116 MIB.add(Cond[i]); in BuildCondBr()
136 assert((Cond.size() <= 3) && in insertBranch()
141 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
148 if (Cond.empty()) in insertBranch()
151 BuildCondBr(MBB, TBB, DL, Cond); in insertBranch()
185 assert( (Cond.size() && Cond.size() <= 3) && in reverseBranchCondition()
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| H A D | MipsInstrInfo.h | 65 SmallVectorImpl<MachineOperand> &Cond,
72 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
77 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
81 SmallVectorImpl<MachineOperand> &Cond,
185 SmallVectorImpl<MachineOperand> &Cond) const;
188 const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FlagsCopyLowering.cpp | 740 X86::CondCode Cond = X86::getCondFromSETCC(MI); in collectCondsInRegs() local
745 CondRegs[Cond] = MI.getOperand(0).getReg(); in collectCondsInRegs()
758 const DebugLoc &TestLoc, X86::CondCode Cond) { in promoteCondToReg() argument
771 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg()
798 X86::CondCode Cond = X86::COND_INVALID; in rewriteArithmetic() local
810 Cond = X86::COND_B; // CF == 1 in rewriteArithmetic()
817 Cond = X86::COND_O; // OF == 1 in rewriteArithmetic()
827 unsigned &CondReg = CondRegs[Cond]; in rewriteArithmetic()
853 X86::CondCode Cond = X86::getCondFromCMov(CMovI); in rewriteCMov() local
921 X86::CondCode Cond = X86::getCondFromBranch(JmpI); in rewriteCondJmp() local
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| H A D | X86InstrCMovSetCC.td | 87 multiclass CMOV_SETCC_Aliases<string Cond, int CC> {
88 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
90 def : InstAlias<"cmov"#Cond#"{w}\t{$src, $dst|$dst, $src}",
92 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
94 def : InstAlias<"cmov"#Cond#"{l}\t{$src, $dst|$dst, $src}",
96 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
98 def : InstAlias<"cmov"#Cond#"{q}\t{$src, $dst|$dst, $src}",
101 def : InstAlias<"set"#Cond#"\t$dst", (SETCCr GR8:$dst, CC), 0>;
102 def : InstAlias<"set"#Cond#"\t$dst", (SETCCm i8mem:$dst, CC), 0>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRInstrInfo.cpp | 306 Cond.clear(); in analyzeBranch()
330 if (Cond.empty()) { in analyzeBranch()
371 Cond.push_back(MachineOperand::CreateImm(BranchCode)); in analyzeBranch()
377 assert(Cond.size() == 1); in analyzeBranch()
401 ArrayRef<MachineOperand> Cond, in insertBranch() argument
408 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
411 if (Cond.empty()) { in insertBranch()
421 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm(); in insertBranch()
467 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
468 assert(Cond.size() == 1 && "Invalid AVR branch condition!"); in reverseBranchCondition()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | GuardUtils.cpp | 66 auto *Cond = BI->getCondition(); in parseWidenableBranch() local
67 if (!Cond->hasOneUse()) in parseWidenableBranch()
73 if (match(Cond, m_Intrinsic<Intrinsic::experimental_widenable_condition>())) { in parseWidenableBranch()
85 if (!match(Cond, m_And(m_Value(A), m_Value(B)))) in parseWidenableBranch()
87 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
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| /freebsd-13.1/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| H A D | ConstraintManager.h | 86 DefinedSVal Cond,
93 ProgramStatePair assumeDual(ProgramStateRef State, DefinedSVal Cond) { in assumeDual() argument
94 ProgramStateRef StTrue = assume(State, Cond, true); in assumeDual()
100 assert(assume(State, Cond, false) && "System is over constrained."); in assumeDual()
105 ProgramStateRef StFalse = assume(State, Cond, false); in assumeDual()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEInstrInfo.cpp | 232 assert((Cond.size() == 3 || Cond.size() == 0) && in insertBranch()
235 if (Cond.empty()) { in insertBranch()
245 assert(Cond[0].isImm() && Cond[2].isReg() && "not implemented"); in insertBranch()
251 unsigned Reg = Cond[2].getReg(); in insertBranch()
252 if (IsIntegerCC(Cond[0].getImm())) { in insertBranch()
269 if (Cond[1].isImm()) { in insertBranch()
272 .add(Cond[1]) // lhs in insertBranch()
273 .add(Cond[2]) // rhs in insertBranch()
277 .add(Cond[0]) in insertBranch()
278 .add(Cond[1]) in insertBranch()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIAnnotateControlFlow.cpp | 83 handleLoopCondition(Value *Cond, PHINode *Broken, llvm::Loop *L,
225 Value *Cond, PHINode *Broken, llvm::Loop *L, BranchInst *Term) { in handleLoopCondition() argument
226 if (Instruction *Inst = dyn_cast<Instruction>(Cond)) { in handleLoopCondition()
235 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
240 if (isa<Constant>(Cond)) { in handleLoopCondition()
241 Instruction *Insert = Cond == BoolTrue ? in handleLoopCondition()
244 Value *Args[] = { Cond, Broken }; in handleLoopCondition()
264 Value *Cond = Term->getCondition(); in handleLoop() local
266 Value *Arg = handleLoopCondition(Cond, Broken, L, Term); in handleLoop()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcInstrInfo.cpp | 154 SmallVectorImpl<MachineOperand> &Cond) { in parseCondBranch() argument
183 parseCondBranch(LastInst, TBB, Cond); in analyzeBranch()
217 parseCondBranch(SecondLastInst, TBB, Cond); in analyzeBranch()
245 ArrayRef<MachineOperand> Cond, in insertBranch() argument
249 assert((Cond.size() == 1 || Cond.size() == 0) && in insertBranch()
253 if (Cond.empty()) { in insertBranch()
260 unsigned CC = Cond[0].getImm(); in insertBranch()
298 SmallVectorImpl<MachineOperand> &Cond) const { in reverseBranchCondition()
299 assert(Cond.size() == 1); in reverseBranchCondition()
300 SPCC::CondCodes CC = static_cast<SPCC::CondCodes>(Cond[0].getImm()); in reverseBranchCondition()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 398 Cond.clear(); in analyzeBranch()
599 if (!Cond.empty() && Cond[0].isImm()) in insertBranch()
603 if (Cond.empty()) { in insertBranch()
1549 if (Cond.empty()) in reverseBranchCondition()
1587 if (Cond.empty() || isNewValueJump(Cond[0].getImm()) || in PredicateInstruction()
3177 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
4268 if (Cond.empty()) in getInvertedPredSense()
4271 Cond[0].setImm(Opc); in getInvertedPredSense()
4443 if (Cond.empty()) in getPredReg()
4446 if (isNewValueJump(Cond[0].getImm()) || Cond[1].isMBB()) { in getPredReg()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Support/ |
| H A D | Parallel.cpp | 68 Cond.notify_all(); in stop()
94 Cond.notify_one(); in add()
102 Cond.wait(Lock, [&] { return Stop || !WorkStack.empty(); }); in work()
115 std::condition_variable Cond; member in llvm::parallel::detail::__anonf3ea7c1d0111::ThreadPoolExecutor
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