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Searched refs:CSR_READ_2 (Results 1 – 25 of 40) sorted by relevance

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/freebsd-13.1/sys/dev/vte/
H A Dif_vte.c365 mid = CSR_READ_2(sc, VTE_MID0L); in vte_get_macaddr()
368 mid = CSR_READ_2(sc, VTE_MID0M); in vte_get_macaddr()
371 mid = CSR_READ_2(sc, VTE_MID0H); in vte_get_macaddr()
414 CSR_READ_2(sc, VTE_MACID)); in vte_attach()
1242 mcr = CSR_READ_2(sc, VTE_MCR0); in vte_mac_config()
1268 CSR_READ_2(sc, VTE_CNT_MECNT0); in vte_stats_clear()
1269 CSR_READ_2(sc, VTE_CNT_MECNT1); in vte_stats_clear()
1274 CSR_READ_2(sc, VTE_CNT_PAUSE); in vte_stats_clear()
1287 CSR_READ_2(sc, VTE_MECISR); in vte_stats_update()
1788 CSR_READ_2(sc, VTE_MISR); in vte_stop()
[all …]
H A Dif_vtevar.h153 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-13.1/sys/dev/ste/
H A Dif_ste.c285 cfg = CSR_READ_2(sc, STE_MACCTL0); in ste_miibus_statchg()
493 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_poll_locked()
525 status = CSR_READ_2(sc, STE_ISR_ACK); in ste_intr()
815 CSR_READ_2(sc, STE_STAT_RX_OCTETS_LO); in ste_stats_clear()
816 CSR_READ_2(sc, STE_STAT_RX_OCTETS_HI); in ste_stats_clear()
817 CSR_READ_2(sc, STE_STAT_RX_FRAMES); in ste_stats_clear()
824 CSR_READ_2(sc, STE_STAT_TX_FRAMES); in ste_stats_clear()
1651 val = CSR_READ_2(sc, STE_MACCTL1); in ste_stop()
1664 CSR_READ_2(sc, STE_ISR_ACK); in ste_stop()
1729 mac = CSR_READ_2(sc, STE_MACCTL1); in ste_restart_tx()
[all …]
H A Dif_stereg.h492 #define CSR_READ_2(sc, reg) \ macro
/freebsd-13.1/sys/dev/an/
H A Dif_an.c856 id = CSR_READ_2(sc, AN_RX_FID); in an_rxeof()
1221 if (CSR_READ_2(sc, AN_LINKSTAT(sc->mpi350)) in an_intr()
1332 CSR_READ_2(sc, AN_RESP0(sc->mpi350)); in an_cmd()
1333 CSR_READ_2(sc, AN_RESP1(sc->mpi350)); in an_cmd()
1334 CSR_READ_2(sc, AN_RESP2(sc->mpi350)); in an_cmd()
1335 s = CSR_READ_2(sc, AN_STATUS(sc->mpi350)); in an_cmd()
1415 len = CSR_READ_2(sc, AN_DATA1); in an_read_record()
1429 *ptr++ = CSR_READ_2(sc, AN_DATA1); in an_read_record()
1534 if (CSR_READ_2(sc, AN_COMMAND(sc->mpi350)) in an_write_record()
1680 *ptr++ = CSR_READ_2(sc, AN_DATA1); in an_read_data()
[all …]
H A Dif_anreg.h52 #define CSR_READ_2(sc, reg) bus_read_2(sc->port_res, reg) macro
/freebsd-13.1/sys/dev/vge/
H A Dif_vgevar.h228 #define CSR_READ_2(sc, reg) \ macro
236 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
243 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-13.1/sys/dev/stge/
H A Dif_stge.c407 *data = CSR_READ_2(sc, STGE_EepromData); in stge_read_eeprom()
545 v = CSR_READ_2(sc, STGE_StationAddress0); in stge_attach()
548 v = CSR_READ_2(sc, STGE_StationAddress1); in stge_attach()
551 v = CSR_READ_2(sc, STGE_StationAddress2); in stge_attach()
1470 status = CSR_READ_2(sc, STGE_IntStatus); in stge_intr()
1476 status = CSR_READ_2(sc, STGE_IntStatusAck); in stge_intr()
1801 status = CSR_READ_2(sc, STGE_IntStatus); in stge_poll()
1892 CSR_READ_2(sc, STGE_FramesAbortXSColls) + in stge_stats_update()
1893 CSR_READ_2(sc, STGE_FramesWEXDeferal)); in stge_stats_update()
2496 mode = CSR_READ_2(sc, STGE_ReceiveMode); in stge_set_filter()
[all …]
H A Dif_stgereg.h99 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-13.1/sys/dev/bwi/
H A Dif_bwivar.h79 #define CSR_READ_2(sc, reg) \ macro
90 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
95 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
100 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
H A Dbwirf.c223 return CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_read()
254 val = CSR_READ_2(sc, BWI_RF_DATA_HI); in bwi_rf_attach()
258 val |= CSR_READ_2(sc, BWI_RF_DATA_LO); in bwi_rf_attach()
785 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL); in bwi_rf_init_bcm2050()
822 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN); in bwi_rf_init_bcm2050()
1283 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_lo_update_11g()
1285 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_lo_update_11g()
1664 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_calc_nrssi_slope_11b()
1666 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX); in bwi_rf_calc_nrssi_slope_11b()
1942 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV); in bwi_rf_calc_nrssi_slope_11g()
[all …]
H A Dbwimac.c176 return CSR_READ_2(sc, data_reg); in bwi_memobj_read_2()
190 ret = CSR_READ_2(sc, BWI_MOBJ_DATA_UNALIGN); in bwi_memobj_read_4()
195 ret |= CSR_READ_2(sc, BWI_MOBJ_DATA); in bwi_memobj_read_4()
737 if (CSR_READ_2(sc, 0x50e) & 0x80) in bwi_mac_dummy_xmit()
742 if (CSR_READ_2(sc, 0x50e) & 0x400) in bwi_mac_dummy_xmit()
747 if ((CSR_READ_2(sc, 0x690) & 0x100) == 0) in bwi_mac_dummy_xmit()
1949 CSR_READ_2(sc, BWI_PHYINFO); /* dummy read */ in bwi_mac_unlock()
H A Dbwiphy.c151 return CSR_READ_2(sc, BWI_PHY_DATA); in bwi_phy_read()
164 val = CSR_READ_2(sc, BWI_PHYINFO); in bwi_phy_attach()
/freebsd-13.1/sys/dev/vr/
H A Dif_vrreg.h755 #define CSR_READ_2(sc, reg) bus_read_2(sc->vr_res, reg) macro
761 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
762 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vr.c263 return (CSR_READ_2(sc, VR_MIIDATA)); in vr_miibus_readreg()
1621 status = CSR_READ_2(sc, VR_ISR); in vr_poll_locked()
1682 status = CSR_READ_2(sc, VR_ISR); in vr_intr()
1708 status = CSR_READ_2(sc, VR_ISR); in vr_int_task()
1746 status = CSR_READ_2(sc, VR_ISR); in vr_int_task()
/freebsd-13.1/sys/dev/rl/
H A Dif_rl.c431 return (CSR_READ_2(sc, rl8139_reg)); in rl_miibus_readreg()
1136 cur_rx = (CSR_READ_2(sc, RL_CURRXADDR) + 16) % RL_RXBUFLEN; in rl_rxeof()
1139 limit = CSR_READ_2(sc, RL_CURRXBUF) % RL_RXBUFLEN; in rl_rxeof()
1328 if (CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_LINK_OK) { in rl_twister_update()
1344 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1373 linktest = CSR_READ_2(sc, RL_CSCFG) & RL_CSCFG_STATUS; in rl_twister_update()
1471 status = CSR_READ_2(sc, RL_ISR); in rl_poll_locked()
1508 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
1529 status = CSR_READ_2(sc, RL_ISR); in rl_intr()
H A Dif_rlreg.h957 #define CSR_READ_2(sc, reg) \ macro
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-13.1/sys/dev/xl/
H A Dif_xl.c393 val = CSR_READ_2(sc, XL_W4_PHY_MGMT); in xl_mii_bitbang_read()
535 if (CSR_READ_2(sc, XL_W0_EE_CMD) & XL_EE_BUSY) in xl_eeprom_wait()
584 word = CSR_READ_2(sc, XL_W0_EE_DATA); in xl_read_eeprom()
751 mediastat = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_setmode()
885 CSR_READ_2(sc, XL_W2_RESET_OPTIONS) | in xl_reset()
2167 status = CSR_READ_2(sc, XL_STATUS); in xl_intr()
2254 status = CSR_READ_2(sc, XL_STATUS); in xl_poll_locked()
2712 CSR_READ_2(sc, XL_W7_BM_PME); in xl_init_locked()
2941 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_ifmedia_sts()
3130 status = CSR_READ_2(sc, XL_W4_MEDIA_STATUS); in xl_watchdog()
[all …]
/freebsd-13.1/sys/dev/fxp/
H A Dif_fxpvar.h247 #define CSR_READ_2(sc, reg) bus_read_2(sc->fxp_res[0], reg) macro
/freebsd-13.1/sys/dev/ale/
H A Dif_alevar.h237 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-13.1/sys/dev/age/
H A Dif_agevar.h243 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-13.1/sys/dev/alc/
H A Dif_alcvar.h268 #define CSR_READ_2(_sc, reg) \ macro
/freebsd-13.1/sys/dev/ipw/
H A Dif_ipwreg.h330 #define CSR_READ_2(sc, reg) \ macro
/freebsd-13.1/sys/dev/my/
H A Dif_myreg.h399 #define CSR_READ_2(sc, reg) \ macro
/freebsd-13.1/sys/dev/lge/
H A Dif_lgereg.h537 #define CSR_READ_2(sc, reg) \ macro

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