Home
last modified time | relevance | path

Searched refs:CPSR (Results 1 – 25 of 35) sorted by relevance

12

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp256 if (*Regs == ARM::CPSR) in HasImplicitCPSRDef()
304 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
384 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
818 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
882 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
910 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
987 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
1002 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
1043 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); in ReduceMBB()
1098 if (BundleMI->killsRegister(ARM::CPSR)) in ReduceMBB()
[all …]
H A DARMInstrThumb.td419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1006 let isCommutable = 1, Uses = [CPSR] in
1103 let isCompare = 1, Defs = [CPSR] in {
1118 } // isCompare = 1, Defs = [CPSR]
1121 let isCompare = 1, Defs = [CPSR] in {
1150 } // isCompare = 1, Defs = [CPSR]
1228 let Defs = [CPSR] in
1309 let Uses = [CPSR] in
1355 /// instruction modifies the CPSR register.
[all …]
H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I) in copyPhysReg()
64 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMBaseInstrInfo.cpp738 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
982 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
985 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2244 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
3080 Instr.readsRegister(ARM::CPSR, TRI)) in optimizeCompareInstr()
3225 if ((*SI)->isLiveIn(ARM::CPSR)) in optimizeCompareInstr()
3232 MI->getOperand(5).setReg(ARM::CPSR); in optimizeCompareInstr()
3244 MI->clearRegisterDeads(ARM::CPSR); in optimizeCompareInstr()
4361 if (Reg == ARM::CPSR) { in getOperandLatencyImpl()
5478 if (CmpMI->modifiesRegister(ARM::CPSR, TRI)) in findCMPToFoldIntoCBZ()
[all …]
H A DARMFastISel.cpp253 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
254 *CPSR = true; in DefinesOptionalPredicate()
291 bool CPSR = false; in AddOptionalDefs() local
292 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
293 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1251 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1274 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1477 .addImm(ARMPred).addReg(ARM::CPSR); in SelectCmp()
1661 .addReg(ARM::CPSR); in SelectSelect()
1669 .addReg(ARM::CPSR); in SelectSelect()
[all …]
H A DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1858 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1861 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
1874 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
1928 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
3687 let Uses = [CPSR] in
3695 let Defs = [CPSR] in {
3855 // CPSR and the implicit def of CPSR is not needed.
4978 Defs = [CPSR] in {
5784 let Defs = [CPSR] in
[all …]
H A DARMInstrThumb2.td726 /// changed to modify CPSR.
1025 let Defs = [CPSR], Uses = [CPSR] in {
1031 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>,
1041 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>,
1055 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>,
2402 // CPSR and the implicit def of CPSR is not needed.
2709 let Uses = [CPSR] in {
2877 /// changed to modify CPSR.
4440 let Defs = [CPSR] in
4476 let Defs = [CPSR] in
[all …]
H A DThumb2ITBlockPass.cpp173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARM.td331 /// Some instructions update CPSR partially, which can add false dependency for
333 /// mapped to a separate physical register. Avoid partial CPSR update for these
337 "Avoid CPSR partial update for OOO execution">;
339 /// Disable +1 predication cost for instructions updating CPSR.
344 "Disable +1 predication cost for instructions updating CPSR">;
H A DARMInstructionSelector.cpp602 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
796 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1136 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMAsmPrinter.cpp1724 .addReg(ARM::CPSR) in emitInstruction()
1780 .addReg(ARM::CPSR) in emitInstruction()
1911 .addReg(ARM::CPSR) in emitInstruction()
1930 .addReg(ARM::CPSR) in emitInstruction()
1945 .addReg(ARM::CPSR) in emitInstruction()
H A DARMExpandPseudoInsts.cpp1080 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1204 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1693 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1716 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1808 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1814 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1836 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2151 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2353 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2548 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()
H A DMVETPAndVPTOptimisationsPass.cpp195 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
204 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
H A DARMLowOverheadLoops.cpp1395 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1425 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1436 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
H A DARMISelLowering.cpp10612 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
10667 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
10768 .addReg(ARM::CPSR); in EmitSjLjDispatchBlock()
11295 .addReg(ARM::CPSR, in EmitLowered__chkstk()
11311 .addReg(ARM::CPSR, in EmitLowered__chkstk()
11354 .addReg(ARM::CPSR); in EmitLowered__dbzchk()
11372 if (mi.readsRegister(ARM::CPSR)) in checkAndUpdateCPSRKill()
11385 if (succ->isLiveIn(ARM::CPSR)) in checkAndUpdateCPSRKill()
11731 copy0MBB->addLiveIn(ARM::CPSR); in EmitInstrWithCustomInserter()
11732 sinkMBB->addLiveIn(ARM::CPSR); in EmitInstrWithCustomInserter()
[all …]
H A DThumb1FrameLowering.cpp419 .addDef(ARM::CPSR) in emitPrologue()
425 .addDef(ARM::CPSR) in emitPrologue()
H A DARMRegisterInfo.td182 def CPSR : ARMReg<0, "cpsr">;
380 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
H A DARMBaseInstrInfo.h557 return MachineOperand::CreateReg(ARM::CPSR,
H A DThumb2InstrInfo.cpp541 !MI.definesRegister(ARM::CPSR)) { in rewriteT2FrameIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp191 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
257 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
H A DARMMCCodeEmitter.cpp311 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
724 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td66 def CPSR : SparcCtrlReg<0, "CPSR">; // Co-processor state register.
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2476 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
9975 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10025 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10032 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10078 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10086 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10473 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
10706 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR) in checkTargetMatchPredicate()
10710 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR && in checkTargetMatchPredicate()
10713 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR && in checkTargetMatchPredicate()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp1025 case Sparc::CPSR: in parseSparcAsmOperand()
1167 RegNo = Sparc::CPSR; in matchRegisterName()

12