4724     SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in getARMCmp()
4881   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSignedALUO()
5026     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT()
5425     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT_CC()
5460   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSELECT_CC()
5567       SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in OptimizeVFPBrcond()
5616     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBRCOND()
5670     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
5679     SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
5696   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerBR_CC()
6176   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerShiftRightParts()
6220   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerShiftLeftParts()
6782   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerSETCCCARRY()
6783   SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), DL, ARM::CPSR,  in LowerSETCCCARRY()
10109   SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);  in LowerFSETCC()
10424         .addReg(ARM::CPSR, RegState::Define)  in SetupEntryBlockForSjLj()
10429         .addReg(ARM::CPSR, RegState::Define)  in SetupEntryBlockForSjLj()
10612       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
10667       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
10671         .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
10683         .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
10703           .addReg(ARM::CPSR, RegState::Define)  in EmitSjLjDispatchBlock()
10768       .addReg(ARM::CPSR);  in EmitSjLjDispatchBlock()
11218     MIB->getOperand(5).setReg(ARM::CPSR);  in EmitStructByval()
11223       .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);  in EmitStructByval()
11295         .addReg(ARM::CPSR,  in EmitLowered__chkstk()
11311         .addReg(ARM::CPSR,  in EmitLowered__chkstk()
11354       .addReg(ARM::CPSR);  in EmitLowered__dbzchk()
11372     if (mi.readsRegister(ARM::CPSR))  in checkAndUpdateCPSRKill()
11374     if (mi.definesRegister(ARM::CPSR))  in checkAndUpdateCPSRKill()
11385       if (succ->isLiveIn(ARM::CPSR))  in checkAndUpdateCPSRKill()
11392   SelectItr->addRegisterKilled(ARM::CPSR, TRI);  in checkAndUpdateCPSRKill()
11729     if (!MI.killsRegister(ARM::CPSR) &&  in EmitInstrWithCustomInserter()
11731       copy0MBB->addLiveIn(ARM::CPSR);  in EmitInstrWithCustomInserter()
11732       sinkMBB->addLiveIn(ARM::CPSR);  in EmitInstrWithCustomInserter()
11788         .addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
11798         .addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
11807       .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
11882       .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);  in EmitInstrWithCustomInserter()
12015     if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {  in AdjustInstrPostInstrSelection()
12039   MO.setReg(ARM::CPSR);  in AdjustInstrPostInstrSelection()
17274       SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in PerformCMOVCombine()
17288       SDValue CPSRGlue = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR,  in PerformCMOVCombine()
19222     return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);  in getRegForInlineAsmConstraint()