Home
last modified time | relevance | path

Searched refs:models (Results 1 – 25 of 73) sorted by relevance

123

/freebsd-12.1/sys/tools/
H A Dmiidevs2h.awk126 models[nmodels, 1] = $2; # oui name
127 models[nmodels, 2] = $3; # model id
128 models[nmodels, 3] = $4; # id
130 printf("#define\tMII_MODEL_%s_%s\t%s\n", models[nmodels, 1],
131 models[nmodels, 2], models[nmodels, 3]) > hfile
133 models[nmodels, 4] = collectline(5, line)
136 models[nmodels, 1], models[nmodels, 2],
137 models[nmodels, 4]) > hfile
/freebsd-12.1/usr.sbin/pc-sysinstall/pc-sysinstall/
H A Dpc-sysinstall.sh230 xkeyboard-models) ${QUERYDIR}/xkeyboard-models.sh
/freebsd-12.1/usr.sbin/pc-sysinstall/doc/
H A Dhelp-index72 xkeyboard-models
73 Return a list of keyboard models that xorg supports
/freebsd-12.1/usr.sbin/pc-sysinstall/backend-query/
H A DMakefile8 xkeyboard-models.sh xkeyboard-variants.sh
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZ.td23 // SystemZ subtarget scheduling models
/freebsd-12.1/contrib/gcc/config/rs6000/
H A Dt-newas2 # different processor models
H A Dt-aix5214 # different processor models
H A Dt-aix4314 # different processor models
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td12 // MCInstPredicate definitions are used by target scheduling models to describe
34 // MCInstPredicate definitions are typically used by scheduling models to
267 // Instances of this class can be used by processor scheduling models to
284 // Used by processor models to describe dependency breaking instructions.
338 // Convenience classes and definitions used by processor scheduling models to
H A DTargetSchedule.td150 // an in-order latency resource. In this case, the scheduler models
176 // separate reservation station. This simply models the size of the
285 // cycle, regardless of latency, which models a fully pipelined processing
/freebsd-12.1/contrib/file/magic/Magdir/
H A Dvacuum-cleaner6 # navigation map for LG robot vacuum cleaner models VR62xx, VR64xx, VR63xx
/freebsd-12.1/contrib/gcc/config/arm/
H A Darm926ejs.md117 ;; The models for load/store instructions do not accurately describe
119 ;; (such as "ldm!"). These models assume that all memory references
H A Darm1026ejs.md154 ;; The models for load/store instructions do not accurately describe
156 ;; (such as "ldm!"). These models assume that all memory references
H A Darm-generic.md40 ; The write_blockage unit models (partially), the fact that reads will stall
H A Darm1136jfs.md279 ;; The models for load/store instructions do not accurately describe
281 ;; These models assume that all memory references hit in dcache. Also,
H A Darm1020e.md154 ;; The models for load/store instructions do not accurately describe
156 ;; (such as "ldm!"). These models assume that all memory references
/freebsd-12.1/usr.sbin/bsdconfig/mouse/include/
H A Dmessages.subr54 msg_logitech_desc="Logitech protocol (old models) (serial)"
66 msg_mouseman_desc="Logitech MouseMan/TrackMan models (serial)"
/freebsd-12.1/lib/libpmc/pmu-events/
H A DREADME102 The mapfile enables multiple CPU models to share a single set of PMU events.
151 i.e the three CPU models use the JSON files (i.e PMU events) listed
/freebsd-12.1/contrib/gcc/config/i386/
H A Dpredicates.md111 /* For certain code models, the symbolic references are known to fit.
122 /* For certain code models, the code is near as well. */
180 constraints for code models differ. */
234 /* For certain code models, the symbolic references are known to fit. */
243 /* For certain code models, the code is near as well. */
281 constraints for code models differ. */
/freebsd-12.1/usr.sbin/bsnmpd/bsnmpd/
H A Dsnmpd.config46 # Security models
52 # Message Processing models
/freebsd-12.1/sys/powerpc/powerpc/
H A Dcpu.c112 static const struct cputab models[] = { variable
278 for (cp = models; cp->version != 0; cp++) { in cpu_feature_setup()
/freebsd-12.1/sys/gnu/dts/arm/
H A Darmada-388-clearfog.dtsi231 * CS1: PIC microcontroller (Pro models)
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td171 // We model fpscr with two registers: FPSCR models the control bits and will be
172 // reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
173 // models the APSR when it's accessed by some special instructions. In such cases
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrFormats.td168 // Fields used for relation models.
/freebsd-12.1/contrib/libxo/doc/
H A Dfaq.rst110 external data models like ODL, which was seen as too hard a

123