Home
last modified time | relevance | path

Searched refs:isUse (Results 1 – 25 of 103) sorted by relevance

12345

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DProcessImplicitDefs.cpp70 if (MO.isReg() && MO.isUse() && MO.readsReg()) in canTurnIntoImplicitDef()
110 if (MO.isUse()) in processImplicitDef()
H A DRegAllocFast.cpp313 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
648 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
676 if (MO.isUse()) in reloadVirtReg()
748 if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) || in handleThroughOperands()
776 if (MO.isUse()) { in handleThroughOperands()
901 if (MO.isUse()) { in allocateInstruction()
913 if (MO.isUse()) { in allocateInstruction()
949 if (MO.isUse()) { in allocateInstruction()
H A DMachineInstr.cpp280 if (NewMO->isUse()) { in addOperand()
832 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
932 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
960 if (MO.isUse()) in readsWritesVirtualRegister()
1040 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1072 if (MO.isUse()) in findTiedOperandIdx()
1077 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1120 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1370 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
1767 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled()
[all …]
H A DTwoAddressInstructionPass.cpp237 if (MO.isUse() && MOReg != SavedReg) in sink3AddrInstruction()
396 if (MO.isUse() && DI->second < LastUse) in noUseAfterLastDef()
507 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
1098 if (MO.isUse()) { in rescheduleKillAboveMI()
1137 if (MO.isUse()) { in rescheduleKillAboveMI()
1400 if (MO.isUse()) { in tryInstructionTransform()
1479 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1618 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1658 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
H A DMachineSink.cpp418 if (!MO.isReg() || !MO.isUse()) in isWorthBreakingCriticalEdge()
624 if (MO.isUse()) { in FindSuccToSinkTo()
636 if (MO.isUse()) continue; in FindSuccToSinkTo()
898 if (MO.isReg() && MO.isUse()) in SinkInstruction()
1088 } else if (MO.isUse()) { in hasRegisterDependency()
H A DLiveIntervals.cpp782 if (MO.isUse()) { in addKillFlags()
854 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
857 return getSpillWeight(isDef, isUse, MBFI, MI.getParent()); in getSpillWeight()
860 float LiveIntervals::getSpillWeight(bool isDef, bool isUse, in getSpillWeight() argument
865 return (isDef + isUse) * (Freq.getFrequency() * Scale); in getSpillWeight()
983 if (MO.isUse()) { in updateAllRanges()
1067 if (MO->isReg() && MO->isUse()) in handleMoveDown()
1353 if (MO->isReg() && !MO->isUse()) in handleMoveUp()
1547 } else if (MO.isUse()) { in repairOldRegInRange()
H A DCriticalAntiDepBreaker.cpp243 if (MO.isUse() && Special) { in PrescanInstruction()
309 if (!MO.isUse()) continue; in ScanInstruction()
618 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
H A DMachineCSE.cpp151 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
222 if (MO.isUse()) in isPhysDefTriviallyDead()
445 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
H A DDeadMachineInstructionElim.cpp160 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
H A DRegisterScavenging.cpp141 if (MO.isUse()) { in determineKillsAndDefs()
211 if (MO.isUse()) { in forward()
545 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) && in scavengeRegister()
H A DReachingDefAnalysis.cpp108 if (MO.isUse()) in processDefs()
H A DExpandPostRAPseudos.cpp80 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
H A DLiveRangeShrink.cpp144 if (MO.isUse()) in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp264 if (MO.isUse()) { in delayHasHazard()
305 assert(Reg.isUse() && "CALL first operand is not a use."); in insertCallDefsUses()
312 assert(Operand1.isUse() && "CALLrr second operand is not a use."); in insertCallDefsUses()
333 if (MO.isUse()) { in insertDefsUses()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp216 if (MO.isUse()) { in delayHasHazard()
242 else if (MO.isUse()) in insertDefsUses()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp250 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead()
259 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) && in getSuperRegDestIfDead()
H A DX86FixupSetCC.cpp114 if ((Op.getReg() == X86::EFLAGS) && (Op.isUse())) in impUsesFlags()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DLiveIntervals.h106 static float getSpillWeight(bool isDef, bool isUse,
111 static float getSpillWeight(bool isDef, bool isUse,
H A DMachineRegisterInfo.h964 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
978 if (Op->isUse()) in advance()
1070 if ((!ReturnUses && op->isUse()) || in defusechain_instr_iterator()
1084 if (Op->isUse()) in advance()
H A DLiveRegUnits.h67 assert(O->isUse() && "Reg operand not a def and not a use"); in accumulateUsedDefed()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp70 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) && in constrainOperandRegClass()
126 if (MO.isUse()) { in constrainSelectedInstRegOperands()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp178 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in INITIALIZE_PASS_DEPENDENCY()
653 if (!MO.isReg() || !MO.isUse()) in runOnMachineFunction()
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill()) in runOnMachineFunction()
H A DHexagonGenPredicate.cpp257 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); in getPredRegFor()
353 if (MO.isReg() && MO.isUse()) in isScalarPred()
374 if (!MO.isReg() || !MO.isUse()) in convertToPredForm()
H A DHexagonSubtarget.cpp243 if (MO.isUse() && !MI->isCopy() && in apply()
354 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) { in adjustSchedDependency()
437 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) { in restoreLatency()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegColoring.cpp71 weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI, in computeWeight()

12345