| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrAnalysis.h | 58 virtual bool isReturn(const MCInst &Inst) const { in isReturn() function 59 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
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| H A D | MCInstrDesc.h | 246 bool isReturn() const { return Flags & (1ULL << MCID::Return); } in isReturn() function
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 201 assert((!MI->isCall() && !MI->isReturn()) && in delayHasHazard() 231 unsigned E = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() in insertDefsUses() 251 if (MI->isCall() || MI->isReturn()) in insertDefsUses()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86PadShortFunction.cpp | 134 assert(ReturnLoc->isReturn() && !ReturnLoc->isCall() && in runOnMachineFunction() 189 if (MI.isReturn() && !MI.isCall()) { in cyclesUntilReturn()
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| H A D | ShadowCallStack.cpp | 210 if (MI.isReturn()) in runOnMachineFunction() 213 if (MI.isReturn() && MI.isCall()) { in runOnMachineFunction() 298 if (MI.isReturn()) { in runOnMachineFunction()
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| H A D | X86InstrControl.td | 22 let isTerminator = 1, isReturn = 1, isBarrier = 1, 271 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 296 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1, 346 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, 391 let isTerminator = 1, isReturn = 1, isBarrier = 1 in { 401 let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
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| H A D | X86VZeroUpper.cpp | 205 bool IsReturn = MI.isReturn(); in processBasicBlock()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | XRayInstrumentation.cpp | 97 if (T.isReturn() && in replaceRetWithPatchableRet() 128 if (T.isReturn() && in prependRetWithPatchableExit()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMOptimizeBarriersPass.cpp | 48 MI->isReturn()); in CanMovePastDMB()
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| H A D | Thumb2ITBlockPass.cpp | 239 (!MI->isBranch() && !MI->isReturn()) ; ++MBBI) { in InsertITInstructions()
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| /freebsd-12.1/contrib/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 35 if (isBranch() || isCall() || isReturn() || isIndirectBranch()) in mayAffectControlFlow()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.cpp | 199 } else if (I->isReturn()) { in analyzeBranch() 210 isJumpOpcode(I->getOpcode()) || I->isReturn())) { in analyzeBranch()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonShuffler.cpp | 348 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in check() 407 if (HexagonMCInstrInfo::getDesc(MCII, Inst0).isReturn()) in check() 409 if (HexagonMCInstrInfo::getDesc(MCII, Inst1).isReturn()) in check()
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| H A D | HexagonMCChecker.cpp | 305 if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) in reportBranchErrors() 316 if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) { in checkHWLoop() 330 if (Desc.isBranch() || Desc.isCall() || Desc.isReturn()) in checkCOFMax1()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPseudo.td | 234 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0, 239 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 245 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0, 298 let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, 353 let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
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| H A D | RDFDeadCode.cpp | 59 if (MI->mayStore() || MI->isBranch() || MI->isCall() || MI->isReturn()) in isLiveInstr()
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrControl.td | 114 let isReturn = 1 in { 132 } // isReturn = 1
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SpeculationHardening.cpp | 293 if (!MI.isReturn() && !MI.isCall()) in instrumentControlFlow() 314 if (MI.isReturn()) in instrumentControlFlow()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | InstrDocsEmitter.cpp | 102 FLAG(isReturn) in EmitInstrDocs()
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| H A D | CodeGenInstruction.h | 235 bool isReturn : 1; variable
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRFrameLowering.cpp | 157 assert(MBBI->getDesc().isReturn() && in emitEpilogue() 524 if (!MBB.empty() && MBB.back().isReturn()) { in runOnMachineFunction()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DbgEntityHistoryCalculator.cpp | 145 if (LastMI == MBB.end() || !LastMI->isReturn()) in getFirstEpilogueInst()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstr64Bit.td | 75 let isReturn = 1, Uses = [LR8, RM] in 108 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 269 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 275 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 280 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 286 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 292 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 298 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.cpp | 266 return (MI->isBranch() || MI->isReturn() || in isBranchRetTrap()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.td | 451 let isBarrier = 1, isReturn = 1, isTerminator = 1 in { 469 } // isBarrier = 1, isReturn = 1, isTerminator = 1 819 let isBarrier = 1, isReturn = 1, isTerminator = 1 in 826 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2], 832 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in
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