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Searched refs:isOptionalDef (Results 1 – 9 of 9) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h96 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
H A DMachineVerifier.cpp1212 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
1222 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp832 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
939 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
H A DARMISelLowering.cpp9599 if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { in AdjustInstrPostInstrSelection()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp237 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters()
326 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
H A DScheduleDAGRRList.cpp1407 if (MCID.OpInfo[i].isOptionalDef()) { in DelayForLiveRegsBottomUp()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp562 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp9094 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()