Home
last modified time | relevance | path

Searched refs:isDef (Results 1 – 25 of 154) sorted by relevance

1234567

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DImplicitNullChecks.cpp286 if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef())) in canReorder()
439 assert(!(DependenceMO.isDef() && in canHoistInst()
598 return MO.isReg() && MO.getReg() && MO.isDef() && in analyzeBlockForNullChecks()
645 assert(MO.isDef() && "Expected def or use"); in insertFaultingInstr()
687 if (!MO.isReg() || !MO.isDef()) in rewriteNullChecks()
697 if (!MO.isReg() || !MO.getReg() || !MO.isDef()) in rewriteNullChecks()
H A DLiveRangeCalc.cpp84 if (!MO.isDef() && !MO.readsReg()) in calculate()
100 if (MO.isDef()) in calculate()
107 if (MO.isDef() && !LI.hasSubRanges()) in calculate()
174 if (!MO.readsReg() || (IsSubRange && MO.isDef())) in extendToUses()
180 if (MO.isDef()) in extendToUses()
192 assert(!MO.isDef() && "Cannot handle PHI def of partial register."); in extendToUses()
200 if (MO.isDef()) in extendToUses()
H A DMachineOperand.cpp91 if (isDef()) in substPhysReg()
126 if (isDef()) in isRenamable()
220 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp, in ChangeToRegister() argument
233 assert(!(isDead && !isDef) && "Dead flag on non-def"); in ChangeToRegister()
234 assert(!(isKill && isDef) && "Kill flag on def"); in ChangeToRegister()
238 IsDef = isDef; in ChangeToRegister()
268 return getReg() == Other.getReg() && isDef() == Other.isDef() && in isIdenticalTo()
332 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
738 OS << (isDef() ? "implicit-def " : "implicit "); in print()
739 else if (PrintDef && isDef()) in print()
[all …]
H A DRenameIndependentSubregs.cpp180 if (!MO.isDef() && !MO.readsReg()) in findComponents()
190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in findComponents()
219 if (!MO.isDef() && !MO.readsReg()) in rewriteOperands()
224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber()) in rewriteOperands()
346 if (!MO.isDef()) in computeMainRangesFixFlags()
H A DLiveRangeEdit.cpp193 if (MO.isDef()) { in foldAsLoad()
291 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && in eliminateDeadDef()
315 else if (MOI->isDef()) in eliminateDeadDef()
325 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MOI->isDef())) || in eliminateDeadDef()
330 if (MOI->isDef()) { in eliminateDeadDef()
H A DMachineInstrBundle.cpp153 if (MO.isDef()) { in finalizeBundle()
301 if (MO.isDef()) in analyzeVirtReg()
306 if (MO.isDef()) in analyzeVirtReg()
348 } else if (MO.isDef()) { in analyzePhysReg()
H A DRegisterScavenging.cpp148 assert(MO.isDef()); in determineKillsAndDefs()
244 assert(MO.isDef()); in forward()
334 if (MO.isDef()) in findSurvivorReg()
629 if (MO.isDef()) { in scavengeVReg()
721 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
725 if (MO.isDef()) { in scavengeFrameVirtualRegsInBlock()
736 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses"); in scavengeFrameVirtualRegsInBlock()
H A DMachineLICM.cpp434 if (!MO.isDef()) { in ProcessMI()
556 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA()
581 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns()
771 if (!MO.isDef() || !MO.isReg() || !MO.getReg()) in SinkIntoLoop()
866 if (MO.isDef()) in calcRegisterCost()
1063 if (!MO.isReg() || !MO.isDef()) in HasLoopPHIUse()
1133 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1232 if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) { in IsProfitableToHoist()
1386 if (MO.isReg() && MO.isDef() && in EliminateCSE()
1488 if (MO.isReg() && MO.isDef() && !MO.isDead()) in Hoist()
H A DVirtRegMap.cpp532 if ((MO.readsReg() && (MO.isDef() || MO.isKill())) || in rewrite()
533 (MO.isDef() && subRegLiveThrough(*MI, PhysReg))) in rewrite()
536 if (MO.isDef()) { in rewrite()
551 assert(MO.isDef()); in rewrite()
559 if (MO.isDef()) { in rewrite()
H A DCriticalAntiDepBreaker.cpp278 if (!MO.isDef()) continue; in ScanInstruction()
357 if (RefOper->isDef() && RefOper->isEarlyClobber()) in isNewRegClobberedByRefs()
368 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs()
374 if (RefOper->isDef()) in isNewRegClobberedByRefs()
622 if (MO.isDef() && Reg != AntiDepReg) in BreakAntiDependencies()
H A DLiveRegUnits.cpp49 if (!O->isDef() || O->isDebug()) in stepBackward()
77 if (!O->isDef() && !O->readsReg()) in accumulate()
H A DDeadMachineInstructionElim.cpp78 if (MO.isReg() && MO.isDef()) { in isDead()
141 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction()
H A DMachineInstr.cpp615 if (MO.isDef()) { in isIdenticalTo()
673 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
714 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs()
986 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1394 if (!Operand.isReg() || Operand.isDef()) in hasComplexRegisterTies()
1473 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print()
1483 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print()
1847 if (!MO.isReg() || !MO.isDef()) in addRegisterDead()
1892 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads()
1932 if (!MO.isReg() || !MO.isDef()) continue; in setPhysRegsDeadExcept()
[all …]
H A DLivePhysRegs.cpp48 if (!O->isDef() || O->isDebug()) in removeDefs()
93 if (O->isDef()) { in stepForward()
293 if (!MO->isReg() || !MO->isDef() || MO->isDebug()) in recomputeLivenessFlags()
H A DMIRCanonicalizerPass.cpp193 if (!MO.isDef()) in rescheduleCanonically()
209 if (!MO.isDef()) in rescheduleCanonically()
605 if (!MO->isDef()) in doVRegRenaming()
620 if (!MO.isDef() && MO.isKill()) { in doDefKillClear()
625 if (MO.isDef() && MO.isDead()) { in doDefKillClear()
H A DAggressiveAntiDepBreaker.cpp241 if (MO.isDef()) in IsImplicitDefUse()
254 if ((MO.isDef() && MI.isRegTiedToUseOperand(i)) || in GetPassthruRegs()
368 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
378 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
421 if (!MO.isReg() || !MO.isDef()) continue; in PrescanInstruction()
721 if (!Q.second.Operand->isDef() || !Q.second.Operand->isEarlyClobber()) in FindSuitableFreeRegisters()
H A DMachineCSE.cpp264 if (!MO.isReg() || MO.isDef()) in hasLivePhysRegDefUses()
282 if (!MO.isReg() || !MO.isDef()) in hasLivePhysRegDefUses()
357 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach()
576 if (!MO.isReg() || !MO.isDef()) in ProcessBlock()
H A DMachineCopyPropagation.cpp385 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() || in forwardUses()
517 if (!MO.isReg() || !MO.isDef()) in CopyPropagateBlock()
559 if (MO.isDef() && !MO.isEarlyClobber()) { in CopyPropagateBlock()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DMachineOperand.h364 bool isDef() const { in isDef() function
730 void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
756 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
763 assert(!(isDead && !isDef) && "Dead flag on non-def");
764 assert(!(isKill && isDef) && "Kill flag on def");
766 Op.IsDef = isDef;
H A DLiveIntervals.h106 static float getSpillWeight(bool isDef, bool isUse,
111 static float getSpillWeight(bool isDef, bool isUse,
H A DMachineRegisterInfo.h965 (!ReturnDefs && op->isDef()) || in defusechain_iterator()
985 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
1071 (!ReturnDefs && op->isDef()) || in defusechain_instr_iterator()
1091 while (Op && ((!ReturnDefs && Op->isDef()) || in advance()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FixupBWInsts.cpp250 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!"); in getSuperRegDestIfDead()
252 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg())) in getSuperRegDestIfDead()
326 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg)) in tryReplaceCopy()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp374 if (!Op.isReg() || !Op.isDef()) in updateDeadsInRange()
501 if (Op.isDef()) { in updateDeadsInRange()
674 assert(MD.isDef()); in split()
730 if (!Op.isReg() || !Op.isDef()) in isPredicable()
766 if (!Op.isReg() || !Op.isDef()) in getReachingDefForPred()
812 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) in canMoveOver()
879 if (!MO.isReg() || !MO.isDef()) in predicateAt()
927 assert(!Op.isDef() && "Not expecting a def"); in renameInRange()
1006 ReferenceMap &Map = Op.isDef() ? Defs : Uses; in predicate()
1007 if (Op.isDef() && Op.isUndef()) { in predicate()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp152 if (MO.isDef()) in repairReg()
213 if (MO.isDef()) in getRepairCost()
286 assert((!MI.isPHI() || !MO.isDef()) && "Need split for phi def?"); in tryAvoidingSplit()
289 if (!MO.isDef()) { in tryAvoidingSplit()
313 assert(MI.isTerminator() && MO.isDef() && in tryAvoidingSplit()
669 bool Before = !MO.isDef(); in RepairingPlacement()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiDelaySlotFiller.cpp211 if (MO.isDef()) { in delayHasHazard()
240 if (MO.isDef()) in insertDefsUses()

1234567