Searched refs:isAssignedRegDep (Results 1 – 10 of 10) sorted by relevance
145 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()160 if (S.isAssignedRegDep() && S.getLatency() == 0 && in EmitInstruction()
423 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()462 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()478 if (I.isAssignedRegDep() && I.getLatency() == 0 && in getZeroLatency()
706 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()715 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
1852 if ((Pred.getLatency() == 0 && Pred.isAssignedRegDep()) || in producesStall()
165 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()194 if (Succ.isAssignedRegDep()) { in ScheduleNodeBottomUp()476 if (Pred.isAssignedRegDep()) { in DelayForLiveRegsBottomUp()
143 assert(!I->isAssignedRegDep() && in releaseSuccessors()
553 if (Pred.isAssignedRegDep()) { in ReleasePredecessors()766 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()835 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()881 if (Succ.isAssignedRegDep()) { in UnscheduleNodeBottomUp()895 if (Succ2.isAssignedRegDep() && Succ2.getReg() == Reg && in UnscheduleNodeBottomUp()1345 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()2833 if (!SuccPred.isAssignedRegDep()) in canClobberReachingPhysRegUse()2991 assert(!Edge.isAssignedRegDep()); in PrescheduleNodesWithMultipleUses()
82 if (TRI && isAssignedRegDep()) in dump()672 if (PredDep.isAssignedRegDep() && in WillCreateCycle()
3471 if (SI.isAssignedRegDep()) in isValidSchedule()
212 bool isAssignedRegDep() const { in isAssignedRegDep() function