| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPC.td | 57 "Enable 64-bit instructions">;
59 "Enable floating-point instructions">;
71 "Enable SPE instructions",
134 "Enable QPX instructions",
137 "Enable VSX instructions",
150 "Enable Power8 direct move instructions",
235 // POPCNTB p5 through p7 popcntb and related instructions
261 // The key column are the non-record-form instructions.
274 // The key column are the record-form instructions.
287 // The key column are the (default) addend-killing instructions.
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| /freebsd-12.1/contrib/subversion/subversion/libsvn_fs_x/ |
| H A D | reps.c | 175 apr_array_header_t *instructions; member
207 const instruction_t *instructions; member
400 result->instructions = apr_array_make(result_pool, 0, in svn_fs_x__reps_builder_create()
582 + builder->instructions->nelts * 2 in svn_fs_x__reps_estimate_size()
751 for (i = 0; i < builder->instructions->nelts; ++i) in svn_fs_x__write_reps_container()
778 instruction_t *instructions; in svn_fs_x__read_reps_container() local
821 instructions in svn_fs_x__read_reps_container()
824 reps->instructions = instructions; in svn_fs_x__read_reps_container()
828 instruction_t *instruction = instructions + i; in svn_fs_x__read_reps_container()
871 + reps->instruction_count * sizeof(*reps->instructions) in svn_fs_x__serialize_reps_container()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | Hexagon.td | 29 "Hexagon ZReg extension instructions">;
32 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
34 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
37 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
40 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
43 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
48 "true", "Hexagon HVX 64B instructions", [ExtensionHVX]>;
50 "true", "Hexagon HVX 128B instructions", [ExtensionHVX]>;
59 "Use memop instructions">;
123 // Generate mapping table to relate non-predicate instructions with their
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARM.td | 40 "Enable VFP3 instructions",
97 " etc) instructions">;
234 // Some processors benefit from using NEON instructions for scalar
279 /// Disable +1 predication cost for instructions updating CPSR.
292 // "normal" call instructions to callees which do not return.
299 // instructions.
331 "instructions">;
407 "v5TExp instructions",
411 "Support ARM v6 instructions",
431 "Support ARM v7 instructions",
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86.td | 62 "Enable SSE instructions">;
64 "Enable SSE2 instructions",
67 "Enable SSE3 instructions",
70 "Enable SSSE3 instructions",
82 "Enable MMX instructions">;
116 "Enable AVX instructions",
119 "Enable AVX2 instructions",
329 // rotate instructions.
362 "Prefer 256-bit AVX instructions">;
400 // Direct Move instructions.
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| H A D | X86InstrFormats.td | 275 // Attributes specific to X86 instructions...
471 // SI - SSE 1 & 2 scalar instructions
519 // PI - SSE 1 & 2 packed instructions
559 // SSI - SSE1 instructions with XS prefix.
560 // PSI - SSE1 instructions with PS prefix.
590 // SDI - SSE2 instructions with XD prefix.
655 // S3SI - SSE3 instructions with XS prefix.
656 // S3DI - SSE3 instructions with XD prefix.
962 // MMXI - MMX instructions with TB prefix.
968 // MMXID - MMX instructions with XD prefix.
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredExynos.td | 17 // Check the shift in arithmetic and logic instructions.
33 // Identify arithmetic instructions without or with limited extension or shift.
58 // Identify logic instructions with limited shift.
71 // Identify more logic instructions with limited shift.
103 // Identify FP instructions.
106 // Identify 128-bit NEON instructions.
109 // Identify instructions that reset a register efficiently.
137 // Identify cheap arithmetic and logic immediate instructions.
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| H A D | AArch64SchedPredicates.td | 17 // Check the extension type in arithmetic instructions.
29 // Check for shifting in extended arithmetic instructions.
56 // Check for shifting in arithmetic and logic instructions.
134 // Identify arithmetic instructions with extend.
140 // Identify arithmetic immediate instructions.
144 // Identify arithmetic instructions with shift.
148 // Identify arithmetic instructions without shift.
152 // Identify logic immediate instructions.
157 // Identify logic instructions with shift.
165 // Identify logic instructions without shift.
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| H A D | AArch64.td | 27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
57 "Enable ARMv8 CRC-32 checksum instructions">;
87 "Enable FP16 FML instructions", [FeatureFullFP16]>;
105 "Enable Scalable Vector Extension (SVE) instructions">;
152 "Use custom handling of cheap instructions">;
156 "Use Exynos specific handling of cheap instructions",
259 "Enable v8.4-A Data Independent Timing instructions">;
283 "Enable v8.4-A RCPC instructions with Immediate Offsets",
329 "true", "Enable Random Number generation instructions" >;
343 "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
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| H A D | AArch64SchedExynosM1.td | 132 // Branch instructions.
142 // Move instructions.
167 // Load instructions.
173 // Store instructions.
179 // FP data instructions.
423 // Branch instructions
434 // Move instructions.
441 // Load instructions.
454 // Store instructions.
526 // ASIMD instructions.
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| H A D | AArch64SchedExynosM3.td | 182 // Branch instructions.
192 // Move instructions.
213 // Load instructions.
219 // Store instructions.
225 // FP data instructions.
479 // Branch instructions
494 // Move instructions.
503 // Load instructions.
516 // Store instructions.
591 // ASIMD instructions.
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| /freebsd-12.1/contrib/gcc/config/rs6000/ |
| H A D | rs6000.opt | 53 Use PowerPC Graphics group optional instructions
69 Use AltiVec instructions
73 Use 4xx half-word multiply instructions
81 Generate load/store multiple instructions
85 Generate string instructions for block moves
109 Generate load/store with update instructions
113 Do not generate fused multiply/add instructions
117 Generate fused multiply/add instructions
183 Generate isel instructions
191 Generate SPE SIMD instructions on E500
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| /freebsd-12.1/contrib/gcc/config/mips/ |
| H A D | 4130.md | 4 ;; The processor issues each 8-byte aligned pair of instructions together,
6 ;; want two instructions to issue in parallel, we need to make sure that the
15 ;; can change the addresses of many instructions.
20 ;; through the function looking for pairs of instructions that could
32 ;; (a) dependent instructions are separated by a non-dependent
35 ;; (b) instructions that use the multiplication unit are separated
36 ;; by non-multiplication instructions; and
38 ;; (c) memory access instructions are separated by non-memory
39 ;; instructions.
41 ;; The idea is to keep conflicting instructions apart wherever possible
|
| H A D | mips.opt | 32 Use PMC-style 'mad' instructions
40 Use Branch Likely instructions, overriding the architecture default
52 Use trap instructions to check for integer divide by zero
60 Use MIPS-DSP instructions
126 Generate floating-point multiply-add instructions
138 Allow the use of hardware floating-point instructions
150 Use MIPS-3D instructions
182 Do not use MIPS-3D instructions
186 Use paired-single floating-point instructions
194 Restrict the use of hardware floating-point instructions to 32-bit operations
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyInstrFormats.td | 28 // Normal instructions. Default instantiation of a WebAssemblyInst.
44 // instructions are used for ISel and all MI passes. The stack versions of the
45 // instructions do not have register operands (they implicitly operate on the
46 // stack), and local.gets and local.sets are explicit. The register instructions
47 // are converted to their corresponding stack instructions before lowering to
50 // there is always an equivalent pair of instructions.
60 // For instructions that have no register ops, so both sets are the same.
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| /freebsd-12.1/contrib/binutils/gas/doc/ |
| H A D | c-mips.texi | 34 generation of MIPS ASE instructions
141 This tells the assembler to accept MIPS-3D instructions.
147 This tells the assembler to accept MDMX instructions.
153 This tells the assembler to accept DSP Release 1 instructions.
160 This tells the assembler to accept DSP Release 2 instructions.
166 This tells the assembler to accept MT instructions.
475 @section Directives for extending MIPS 16 bit instructions
526 instructions from being accepted.
543 instructions from being accepted.
551 Release 1 instructions from being accepted.
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| H A D | c-i386.texi | 201 @cindex return instructions, i386
203 @cindex return instructions, x86-64
259 @cindex conversion instructions, i386
260 @cindex i386 conversion instructions
262 @cindex x86-64 conversion instructions
290 instructions.
292 @cindex jump instructions, i386
293 @cindex call instructions, i386
294 @cindex jump instructions, x86-64
295 @cindex call instructions, x86-64
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| /freebsd-12.1/usr.bin/bc/ |
| H A D | bc.y | 100 static struct tree *instructions = NULL; variable
776 free(instructions);
779 instructions = p;
790 instructions[current].u.cstr = str; in cs()
801 if (instructions[current].u.astr == NULL) in as()
816 instructions[current++].index = arg; in node()
821 instructions[current++].index = arg; in node()
834 if (instructions[i].index >= 0) { in emit()
836 instructions[i].index != i) { in emit()
841 fputs(instructions[i].u.cstr, stdout); in emit()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPU.td | 55 "Have global_* flat memory instructions"
144 "Additional instructions for CI+"
150 "Additional instructions for VI+"
156 "Additional instructions for GFX9+"
174 "Has i16/f16 instructions"
180 "Has VOP3P packed instructions"
186 "Has v_movrel*_b32 instructions"
198 "Has store scalar memory instructions"
264 "Has unpacked d16 vmem instructions"
276 "Has v_dot* instructions"
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| H A D | SISchedule.td | 28 // Vector ALU instructions
41 // Half rate 64-bit instructions.
44 // FIXME: Should there be a class for instructions which are VALU
45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
46 // instructions)
50 // MicroOpBufferSize = 1 means that instructions will always be added
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| /freebsd-12.1/contrib/gcc/config/arm/ |
| H A D | arm1026ejs.md | 31 ;; instructions is "true", i.e., that all of the instructions are
60 ;; ALU instructions require three cycles to execute, and use the ALU
92 ;; Multiplication instructions loop in the execute stage until the
96 ;; The result of the "smul" and "smulw" instructions is not available
119 ;; The "muls" and "mlas" instructions loop in the execute stage for
127 ;; Long multiply instructions that produce two registers of
130 ;; word. That fact is not modeled; instead, the instructions are
134 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
154 ;; The models for load/store instructions do not accurately describe
159 ;; LSU instructions require six cycles to execute. They use the ALU
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| H A D | arm1020e.md | 31 ;; instructions is "true", i.e., that all of the instructions are
60 ;; ALU instructions require three cycles to execute, and use the ALU
92 ;; Multiplication instructions loop in the execute stage until the
96 ;; The result of the "smul" and "smulw" instructions is not available
119 ;; The "muls" and "mlas" instructions loop in the execute stage for
127 ;; Long multiply instructions that produce two registers of
130 ;; word. That fact is not modeled; instead, the instructions are
134 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
154 ;; The models for load/store instructions do not accurately describe
159 ;; LSU instructions require six cycles to execute. They use the ALU
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| /freebsd-12.1/contrib/binutils/opcodes/ |
| H A D | arc-ext.c | 49 if (!arc_extension_map.instructions[opcode]) in arcExtMap_instName()
51 *flags = arc_extension_map.instructions[opcode]->flags; in arcExtMap_instName()
52 return arc_extension_map.instructions[opcode]->name; in arcExtMap_instName()
127 insn = arc_extension_map.instructions[i]; in cleanup_ext_map()
193 arc_extension_map.instructions[(int) opcode] = insn; in arcExtMap_add()
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| /freebsd-12.1/contrib/subversion/subversion/libsvn_delta/ |
| H A D | svndiff.c | 167 svn_stringbuf_t *instructions; in encode_window() local
174 instructions = svn_stringbuf_create_empty(pool); in encode_window()
205 SVN_ERR(svn__compress_lz4(instructions->data, instructions->len, in encode_window()
207 instructions = compressed_instructions; in encode_window()
213 SVN_ERR(svn__compress_zlib(instructions->data, instructions->len, in encode_window()
215 instructions = compressed_instructions; in encode_window()
217 append_encoded_int(header, instructions->len); in encode_window()
241 *instructions_p = instructions; in encode_window()
255 svn_stringbuf_t *instructions; in window_handler() local
291 if (instructions->len > 0) in window_handler()
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| /freebsd-12.1/contrib/gcc/config/i386/ |
| H A D | ppro.md | 57 ;; - Find a less crude way to model complex instructions, in
71 ;; Simple instructions of the register-register form have only one uop.
72 ;; Load instructions are also only one uop. Store instructions decode to
73 ;; two uops, and simple read-modify instructions also take two uops.
75 ;; Simple read-modify-write instructions have four uops. The rules for
96 ;; Most instructions can be decoded on any of the three decoders.
122 ;; Only the irregular instructions have to be modeled here. A load
126 ;; The simple instructions follow a very regular pattern of 1 uop per
447 ;; MMX instructions can execute on either port 0 or port 1 with a
497 ;; ??? I assumed that all SSE instructions decode on decoder0,
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