Lines Matching refs:instructions
57 "Enable 64-bit instructions">;
59 "Enable floating-point instructions">;
65 "Enable classic FPU instructions",
68 "Enable Altivec instructions",
71 "Enable SPE instructions",
102 "Enable the fri[mnpz] instructions",
105 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
112 "Enable extended divide instructions">;
120 "Enable Book E instructions",
126 "Enable E500/E500mc instructions">;
130 "Enable PPC 4xx instructions">;
132 "Enable PPC 6xx instructions">;
134 "Enable QPX instructions",
137 "Enable VSX instructions",
140 "Enable POWER8 Altivec instructions",
143 "Enable POWER8 Crypto instructions",
146 "Enable POWER8 vector instructions",
150 "Enable Power8 direct move instructions",
162 "Enable Hardware Transactional Memory instructions">;
173 "Enable the popcnt[dw] instructions">;
175 // default. These processors do support the instructions, but they're
179 "Has slow popcnt[dw] instructions">;
182 "Treat vector data stream cache control instructions as deprecated">;
184 def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
186 "Enable instructions added in ISA 3.0.">;
188 "Enable POWER9 Altivec instructions",
191 "Enable POWER9 vector instructions",
234 // DFP p6, p6x, p7 decimal floating-point instructions
235 // POPCNTB p5 through p7 popcntb and related instructions
240 // RecFormRel - Filter class used to relate non-record-form instructions with
261 // The key column are the non-record-form instructions.
274 // The key column are the record-form instructions.
287 // The key column are the (default) addend-killing instructions.
474 // Information about the instructions.