Searched refs:has16BitInsts (Results 1 – 7 of 7) sorted by relevance
413 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()418 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()497 if (EltSize == 16 && Index == 0 && ST->has16BitInsts()) in getVectorInstrCost()
756 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBinaryOperator()848 if (ST->has16BitInsts() && needsPromotionToI32(I.getOperand(0)->getType()) && in visitICmpInst()858 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitSelectInst()877 if (ST->has16BitInsts() && needsPromotionToI32(I.getType()) && in visitBitreverseIntrinsicInst()
646 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); in isFPImmLegal()760 (Subtarget->has16BitInsts() && VT == MVT::f16); in isFAbsFree()766 (Subtarget->has16BitInsts() && VT == MVT::f16) || in isFNegFree()803 if (DestSize== 16 && Subtarget->has16BitInsts()) in isTruncateFree()813 if (SrcSize == 16 && Subtarget->has16BitInsts()) in isZExtFree()2462 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerUINT_TO_FP()2489 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { in LowerSINT_TO_FP()2643 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) { in LowerFP_TO_SINT()2666 if (Subtarget->has16BitInsts() && SrcVT == MVT::f16) { in LowerFP_TO_UINT()3203 if (Subtarget->has16BitInsts() && VT.getScalarType().bitsLE(MVT::i16)) in performMulCombine()[all …]
142 bool has16BitInsts() const { in has16BitInsts() function
140 if (Subtarget->has16BitInsts()) { in SITargetLowering()349 if (Subtarget->has16BitInsts()) { in SITargetLowering()421 if (Subtarget->has16BitInsts()) { in SITargetLowering()640 if (Subtarget->has16BitInsts()) { in SITargetLowering()752 if (Size == 16 && Subtarget->has16BitInsts()) in getRegisterTypeForCallingConv()773 if (Size == 16 && Subtarget->has16BitInsts()) in getNumRegistersForCallingConv()805 if (Size == 16 && Subtarget->has16BitInsts()) { in getVectorTypeBreakdownForCallingConv()1254 if (Subtarget->has16BitInsts() && VT == MVT::i16) { in isTypeDesirableForOp()3565 return Subtarget->has16BitInsts() && Subtarget->hasFP16Denormals(); in isFMAFasterThanFMulAndFAdd()7654 if (!Subtarget->has16BitInsts() || in performZeroExtendCombine()[all …]
734 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
2443 return ST.has16BitInsts() && in isInlineConstant()2488 return ST.has16BitInsts() && in isInlineConstant()2498 return ST.has16BitInsts() && in isInlineConstant()2502 return ST.has16BitInsts() && in isInlineConstant()