| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypes.h | 281 return DAG.getZeroExtendInReg(Op, dl, OldVT.getScalarType()); in ZExtPromotedInteger()
295 return DAG.getZeroExtendInReg(Op, DL, OldVT.getScalarType()); in SExtOrZExtPromotedInteger()
|
| H A D | LegalizeDAG.cpp | 537 Value = DAG.getZeroExtendInReg(Value, dl, StVT); in LegalizeStoreOps()
926 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); in LegalizeLoadOps()
2766 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
2770 LHS = DAG.getZeroExtendInReg(Res, dl, AtomicType); in ExpandNode()
2771 RHS = DAG.getZeroExtendInReg(Node->getOperand(2), dl, AtomicType); in ExpandNode()
|
| H A D | LegalizeIntegerTypes.cpp | 525 return DAG.getZeroExtendInReg(Res, dl, in PromoteIntRes_INT_EXTEND()
878 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT); in PromoteIntRes_UADDSUBO()
1425 return DAG.getZeroExtendInReg(Op, dl, in PromoteIntOp_ZERO_EXTEND()
3127 Hi = DAG.getZeroExtendInReg(Hi, dl, in ExpandIntRes_ZERO_EXTEND()
|
| H A D | DAGCombiner.cpp | 1151 return DAG.getZeroExtendInReg(NewOp, DL, OldVT); in ZExtPromoteOperand()
8896 Op = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
8908 SDValue And = DAG.getZeroExtendInReg(Op, SDLoc(N), MinVT.getScalarType()); in visitZERO_EXTEND()
9561 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT.getScalarType()); in visitSIGN_EXTEND_INREG()
18632 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), VT); in SimplifySelectCC()
|
| H A D | TargetLowering.cpp | 1074 Op, TLO.DAG.getZeroExtendInReg(Op0, dl, ExVT.getScalarType())); in SimplifyDemandedBits()
|
| H A D | SelectionDAG.cpp | 1127 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT) { in getZeroExtendInReg() function in SelectionDAG
|
| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 964 Victim = DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
974 : DAG.getZeroExtendInReg(Victim, dl, MVT::i8); in LowerShifts()
|
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 1197 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1427 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
|
| H A D | AMDGPUISelLowering.cpp | 3935 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
|
| H A D | SIISelLowering.cpp | 6416 Cvt = DAG.getZeroExtendInReg(NewLoad, SL, TruncVT); in widenLoad()
|
| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 790 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
|
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 2159 Vs[i] = DAG.getZeroExtendInReg(Vs[i], dl, MVT::i8); in buildVector32()
2314 ExtV = DAG.getZeroExtendInReg(VecV, dl, tyScalar(ValTy)); in extractVector()
|
| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 36090 return DAG.getZeroExtendInReg(Op, DL, NarrowVT.getScalarType()); in PromoteMaskArithmetic()
39503 Res = DAG.getZeroExtendInReg(Res, dl, N0.getValueType().getScalarType()); in combineExtSetcc()
|