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Searched refs:getTargetExtractSubreg (Results 1 – 18 of 18) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp469 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, VecTy, S); in buildHvxVectorReg()
539 return DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, P); in createHvxPrefixPred()
542 return DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, P); in createHvxPrefixPred()
780 VecV = DAG.getTargetExtractSubreg(SubIdx, dl, VecTy, VecV); in extractHvxSubvectorReg()
885 V0 = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, VecV); in insertHvxSubvectorReg()
886 V1 = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, VecV); in insertHvxSubvectorReg()
932 SDValue R0 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, V); in insertHvxSubvectorReg()
933 SDValue R1 = DAG.getTargetExtractSubreg(Hexagon::isub_hi, dl, MVT::i32, V); in insertHvxSubvectorReg()
1390 return DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, ResTy, Pair); in LowerHvxMulh()
1393 return DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, ResTy, Pair); in LowerHvxMulh()
H A DHexagonISelDAGToDAGHVX.cpp1016 Op = DAG.getTargetExtractSubreg(Sub, dl, HalfTy, Op); in materialize()
1407 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_lo, dl, SingleTy, Vec); in scalarizeShuffle()
1409 Vec = DAG.getTargetExtractSubreg(Hexagon::vsub_hi, dl, SingleTy, Vec); in scalarizeShuffle()
H A DHexagonISelLowering.cpp2290 T1 = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, T1); in extractVector()
2312 ExtV = DAG.getTargetExtractSubreg(SubIdx, dl, MVT::i32, VecV); in extractVector()
2357 ValR = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, ValR); in insertVector()
2510 W = DAG.getTargetExtractSubreg(Hexagon::isub_lo, dl, MVT::i32, W); in LowerCONCAT_VECTORS()
H A DHexagonISelDAGToDAG.cpp521 Value = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, in SelectIndexedStore()
796 SDValue E = CurDAG->getTargetExtractSubreg(Hexagon::isub_lo, dl, ResTy, in SelectVAlign()
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp244 SDValue Sub0 = CurDAG->getTargetExtractSubreg(SP::sub_even, dl, MVT::i32, in tryInlineAsm()
246 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm()
H A DSparcISelLowering.cpp2705 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, in LowerF64Op()
2707 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, in LowerF64Op()
2855 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, in LowerFNEGorFABS()
2857 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, in LowerFNEGorFABS()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp1206 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectLoad()
1242 CurDAG->getTargetExtractSubreg(SubRegIdx + i, dl, VT, SuperReg)); in SelectPostLoad()
1321 return DAG.getTargetExtractSubreg(AArch64::dsub, SDLoc(V128Reg), NarrowTy, in NarrowVector()
1354 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, SuperReg); in SelectLoadLane()
1406 SDValue NV = CurDAG->getTargetExtractSubreg(QSubs[i], dl, WideVT, in SelectPostLoadLane()
2860 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT, in Select()
H A DAArch64ISelLowering.cpp4578 return DAG.getTargetExtractSubreg(AArch64::hsub, DL, VT, Sel); in LowerFCOPYSIGN()
4580 return DAG.getTargetExtractSubreg(AArch64::ssub, DL, VT, Sel); in LowerFCOPYSIGN()
4582 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, VT, Sel); in LowerFCOPYSIGN()
5914 return DAG.getTargetExtractSubreg(AArch64::dsub, DL, NarrowTy, V128Reg); in NarrowVector()
11492 Results.push_back(DAG.getTargetExtractSubreg(SubReg1, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
11494 Results.push_back(DAG.getTargetExtractSubreg(SubReg2, SDLoc(N), MVT::i64, in ReplaceCMP_SWAP_128Results()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1874 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLD()
2150 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg)); in SelectVLDSTLane()
2277 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg)); in SelectVLDDup()
4234 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32, in tryInlineAsm()
4236 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32, in tryInlineAsm()
H A DARMISelLowering.cpp7939 DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_1 : ARM::gsub_0, in ReplaceCMP_SWAP_64Results()
7942 DAG.getTargetExtractSubreg(isBigEndian ? ARM::gsub_0 : ARM::gsub_1, in ReplaceCMP_SWAP_64Results()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp2371 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2372 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
2920 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, in lowerBITCAST()
2929 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
4913 SDValue Hi = DAG.getTargetExtractSubreg(SystemZ::subreg_h64, in lowerGR128ToI128()
4915 SDValue Lo = DAG.getTargetExtractSubreg(SystemZ::subreg_l64, in lowerGR128ToI128()
H A DSystemZISelDAGToDAG.cpp938 return CurDAG->getTargetExtractSubreg(SystemZ::subreg_l32, DL, VT, N); in convertTo()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1233 SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT,
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp3828 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result); in Select()
3995 Reg = CurDAG->getTargetExtractSubreg(SubRegOp, dl, VT, Reg); in Select()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp1757 = CurDAG->getTargetExtractSubreg(SubReg, SL, VT, SDValue(CmpSwap, 0)); in SelectATOMIC_CMP_SWAP()
H A DSIISelLowering.cpp9403 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr); in buildRSRC()
9404 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr); in buildRSRC()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4838 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg); in Select()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp7821 SDValue SelectionDAG::getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, in getTargetExtractSubreg() function in SelectionDAG