| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 71 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | X86RegisterInfo.cpp | 88 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in X86RegisterInfo
96 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
105 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi); in getMatchingSuperRegClass()
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| H A D | X86InstructionSelector.cpp | 749 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in selectTruncOrPtrToInt()
1214 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx); in emitExtractSubreg()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 61 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | AArch64RegisterInfo.cpp | 98 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg() function in AArch64RegisterInfo
107 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx); in getSubClassWithSubReg()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 470 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
483 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
589 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
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| H A D | FastISel.cpp | 2227 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); in fastEmitInst_extractsubreg()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIFormMemoryClauses.cpp | 156 if (TRI->getSubClassWithSubReg(RC, Idx) != RC) in forAllLanes()
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| H A D | SIInstrInfo.h | 756 assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg( in getOpSize()
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| H A D | AMDGPUISelDAGToDAG.cpp | 337 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC, in getOperandRegClass()
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| H A D | SIInstrInfo.cpp | 3675 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg( in legalizeGenericOperand()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 376 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() function
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| H A D | CodeGenRegisters.cpp | 993 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx); in getMatchingSubClassWithSubRegs()
1528 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
2220 if (RC->getSubClassWithSubReg(&SubIdx) != RC) in inferMatchingSuperRegClass()
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| H A D | RegisterInfoEmitter.cpp | 1476 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 577 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { in getSubClassWithSubReg() function
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 475 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
485 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
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| H A D | MachineInstr.cpp | 896 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
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| H A D | SplitKit.cpp | 564 if (TRI.getSubClassWithSubReg(RC, Idx) != RC) in buildCopy()
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| H A D | MachineVerifier.cpp | 1383 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
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