Searched refs:getSpillAlignment (Results 1 – 19 of 19) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 47 TRI.getSpillAlignment(RC), true); in createLRSpillSlot() 61 TRI.getSpillAlignment(RC), true); in createFPSpillSlot() 74 unsigned Align = TRI.getSpillAlignment(RC); in createEHSpillSlot()
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| H A D | XCoreFrameLowering.cpp | 586 unsigned Align = TRI.getSpillAlignment(RC); in processFunctionBeforeFrameFinalized()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 64 TRI.getSpillAlignment(RC), false); in createEhDataRegsFI() 78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); in createISRRegFI() 101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); in getMoveF64ViaSpillFI()
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| H A D | MipsSEFrameLowering.cpp | 896 TRI->getSpillAlignment(RC), in determineCalleeSaves() 913 TRI->getSpillAlignment(RC), in determineCalleeSaves()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 127 HRI.getSpillAlignment(VecRC)); in runOnMachineFunction()
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| H A D | HexagonFrameLowering.cpp | 1532 unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment()); in assignCalleeSavedSpillSlots() 1756 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec2() 1803 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec2() 1842 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec() 1870 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec() 1966 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC); in determineCalleeSaves()
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| H A D | HexagonInstrInfo.cpp | 882 unsigned RegAlign = TRI->getSpillAlignment(*RC); in storeRegToStackSlot() 948 unsigned RegAlign = TRI->getSpillAlignment(*RC); in loadRegFromStackSlot()
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| H A D | HexagonISelLowering.cpp | 440 unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in LowerCall()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 259 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 326 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment() function
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 97 unsigned Align = TRI->getSpillAlignment(*RC); in createSpillSlot()
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| H A D | RegisterScavenging.cpp | 469 unsigned NeedAlign = TRI->getSpillAlignment(RC); in spill()
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| H A D | PrologEpilogInserter.cpp | 389 unsigned Align = RegInfo->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
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| H A D | RegAllocFast.cpp | 246 unsigned Align = TRI->getSpillAlignment(RC); in getStackSpaceFor()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 423 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2069 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 1959 unsigned Align = TRI.getSpillAlignment(RC); in addScavengingSpillSlot()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2021 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 2009 unsigned Align = TRI->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
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