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Searched refs:getSpillAlignment (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreMachineFunctionInfo.cpp47 TRI.getSpillAlignment(RC), true); in createLRSpillSlot()
61 TRI.getSpillAlignment(RC), true); in createFPSpillSlot()
74 unsigned Align = TRI.getSpillAlignment(RC); in createEHSpillSlot()
H A DXCoreFrameLowering.cpp586 unsigned Align = TRI.getSpillAlignment(RC); in processFunctionBeforeFrameFinalized()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsMachineFunction.cpp64 TRI.getSpillAlignment(RC), false); in createEhDataRegsFI()
78 TRI.getSpillSize(RC), TRI.getSpillAlignment(RC), false); in createISRRegFI()
101 TRI.getSpillSize(*RC), TRI.getSpillAlignment(*RC), false); in getMoveF64ViaSpillFI()
H A DMipsSEFrameLowering.cpp896 TRI->getSpillAlignment(RC), in determineCalleeSaves()
913 TRI->getSpillAlignment(RC), in determineCalleeSaves()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonVExtract.cpp127 HRI.getSpillAlignment(VecRC)); in runOnMachineFunction()
H A DHexagonFrameLowering.cpp1532 unsigned Align = std::min(TRI->getSpillAlignment(*RC), getStackAlignment()); in assignCalleeSavedSpillSlots()
1756 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec2()
1803 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec2()
1842 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandStoreVec()
1870 unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in expandLoadVec()
1966 unsigned S = HRI.getSpillSize(*RC), A = HRI.getSpillAlignment(*RC); in determineCalleeSaves()
H A DHexagonInstrInfo.cpp882 unsigned RegAlign = TRI->getSpillAlignment(*RC); in storeRegToStackSlot()
948 unsigned RegAlign = TRI->getSpillAlignment(*RC); in loadRegFromStackSlot()
H A DHexagonISelLowering.cpp440 unsigned VecAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass); in LowerCall()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVFrameLowering.cpp259 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h326 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment() function
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DVirtRegMap.cpp97 unsigned Align = TRI->getSpillAlignment(*RC); in createSpillSlot()
H A DRegisterScavenging.cpp469 unsigned NeedAlign = TRI->getSpillAlignment(RC); in spill()
H A DPrologEpilogInserter.cpp389 unsigned Align = RegInfo->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()
H A DRegAllocFast.cpp246 unsigned Align = TRI->getSpillAlignment(RC); in getStackSpaceFor()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp423 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlignment(*RC), false); in processFunctionBeforeFrameFinalized()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp2069 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1959 unsigned Align = TRI.getSpillAlignment(RC); in addScavengingSpillSlot()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp2021 unsigned Align = TRI->getSpillAlignment(RC); in determineCalleeSaves()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp2009 unsigned Align = TRI->getSpillAlignment(*RC); in assignCalleeSavedSpillSlots()