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Searched refs:getRegClassFor (Results 1 – 25 of 29) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp95 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
132 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
328 && TLI->getRegClassFor(VT) in rawRegPressureDelta()
329 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
339 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
340 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
476 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
487 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
H A DInstrEmitter.cpp109 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
168 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()
230 TLI->getRegClassFor(Node->getSimpleValueType(i)); in CreateVirtualRegisters()
294 TLI->getRegClassFor(Op.getSimpleValueType()); in getVR()
400 TLI->isTypeLegal(OpVT) ? TLI->getRegClassFor(OpVT) : nullptr; in AddOperand()
483 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
518 TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
588 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getSimpleValueType(0)); in EmitSubregNode()
H A DFunctionLoweringInfo.cpp357 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT)); in CreateReg()
540 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateSwiftErrorVReg()
559 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in getOrCreateSwiftErrorVRegDefAt()
H A DFastISel.cpp446 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeConstant()
943 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
1555 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT); in selectBitCast()
1556 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); in selectBitCast()
2223 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in fastEmitInst_extractsubreg()
H A DSelectionDAGISel.cpp1171 TLI->getRegClassFor(TLI->getPointerTy(CurDAG->getDataLayout())); in PrepareEHLandingPad()
1281 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in createSwiftErrorEntriesInEntryBlock()
1443 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL)); in propagateSwiftErrorVRegs()
H A DSelectionDAGBuilder.cpp6224 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT); in visitIntrinsicCall()
7743 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) { in visitInlineAsm()
9166 unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT)); in LowerArguments()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp404 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()
414 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()
440 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
456 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()
520 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()
627 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()
678 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); in fastMaterializeAlloca()
984 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
995 RC = TLI.getRegClassFor(VT); in ARMEmitLoad()
1586 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); in SelectIToFP()
[all …]
H A DARMISelLowering.h457 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FastISel.cpp2040 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitCMoveSelect()
2228 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitSSESelect()
2365 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86FastEmitPseudoSelect()
2393 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); in X86SelectSelect()
2463 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); in X86SelectIntToFP()
2852 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerIntrinsicCall()
2936 ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3062 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3147 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); in fastLowerArguments()
3746 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in X86MaterializeInt()
[all …]
H A DX86ISelLowering.cpp608 if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) { in X86TargetLowering()
618 if (UseX87 && getRegClassFor(MVT::f64) == &X86::RFP64RegClass) { in X86TargetLowering()
3311 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrTy)); in LowerFormalArguments()
21031 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy); in LowerDYNAMIC_STACKALLOC()
27845 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); in EmitVAARG64WithCustomInserter()
27846 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); in EmitVAARG64WithCustomInserter()
28638 getRegClassFor(getPointerTy(MF->getDataLayout())); in EmitLoweredSegAlloca()
29024 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitSetJmpShadowStackFix()
29128 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitEHSjLjSetJmp()
29225 const TargetRegisterClass *PtrRC = getRegClassFor(PVT); in emitLongJmpShadowStackFix()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1545 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitSignExtendToI32InReg()
1564 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicBinaryPartword()
1567 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicBinaryPartword()
1775 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in emitAtomicCmpSwapPartword()
1778 getRegClassFor(ArePtrs64bit ? MVT::i64 : MVT::i32); in emitAtomicCmpSwapPartword()
2330 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in lowerRETURNADDR()
3445 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
3850 RC = getRegClassFor(VT); in parseRegForInlineAsmConstraint()
3862 RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT); in parseRegForInlineAsmConstraint()
4131 const TargetRegisterClass *RC = getRegClassFor(RegTy); in copyByValRegs()
[all …]
H A DMipsSEISelDAGToDAG.cpp1242 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect()
1310 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple); in trySelect()
H A DMipsFastISel.cpp1295 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp262 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT); in analyzeMustTailForwardedRegisters()
H A DMachineScheduler.cpp2731 TLI->getRegClassFor(LegalIntVT)); in initPolicy()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp416 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
429 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
449 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP()
535 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
2912 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3145 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); in finishCall()
3601 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
3767 ResultReg1 = createResultReg(TLI.getRegClassFor(VT)); in fastLowerIntrinsicCall()
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp516 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerCCCArguments()
1071 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64); in EmitSubregExt()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1522 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT); in finishCall()
1531 ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in finishCall()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp836 MF.getRegInfo().createVirtualRegister(getRegClassFor(PtrVT)); in LowerFormalArguments()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp738 const TargetRegisterClass *RC = getRegClassFor(RegVT); in LowerFormalArguments()
982 unsigned Reg = MF.addLiveIn(HRI.getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp694 getRegClassFor(MVT::i16)); in LowerCCCArguments()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp512 unsigned Reg = MF.addLiveIn(RI.getRARegister(), getRegClassFor(XLenVT)); in lowerRETURNADDR()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetLowering.h622 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const { in getRegClassFor() function
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp601 getRegClassFor(VA.getLocVT())); in LowerFormalArguments_64()
2673 unsigned RetReg = MF.addLiveIn(SP::I7, TLI.getRegClassFor(PtrVT)); in LowerRETURNADDR()

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