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Searched refs:getDesc (Results 1 – 25 of 135) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h316 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
324 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
340 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
446 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
478 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
488 return MI.getDesc().TSFlags & SIInstrFlags::EXP; in isEXP()
496 return MI.getDesc().TSFlags & SIInstrFlags::WQM; in isWQM()
528 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
606 return MI.getDesc().TSFlags & ClampFlags; in getClampMask()
644 if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) { in isInlineConstant()
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp230 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
238 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
261 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
270 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
316 MCInst const &ID = ISJ->getDesc(); in check()
348 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in check()
396 if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) in check()
431 MCInst const &ID = ISJ->getDesc(); in check()
439 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in check()
575 MCInst const &ID = ISJ->getDesc(); in check()
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H A DHexagonMCInstrInfo.cpp213 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
220 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
288 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
306 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
312 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
351 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
508 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) || in isConstExtended()
510 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch())) in isConstExtended()
530 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && in isCanon()
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H A DHexagonMCChecker.cpp89 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
304 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
315 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
329 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
417 bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch(); in checkNewValues()
457 HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer)); in checkNewValues()
498 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
515 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
531 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
556 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
H A DHexagonMCShuffler.cpp43 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
65 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
88 MCInst const &MI = I->getDesc(); in copyTo()
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp186 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
233 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
234 J->getDesc().isIndirectBranch()) { in analyzeBranch()
250 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
258 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
264 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
271 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
289 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
290 !I->getDesc().isConditionalBranch()) in removeBranch()
303 if (!I->getDesc().isConditionalBranch()) in removeBranch()
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/freebsd-12.1/contrib/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp42 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isAvailable()
70 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
94 Resources->releaseBuffers(Inst.getDesc().Buffers); in issueInstruction()
142 const InstrDesc &D = IR.getInstruction()->getDesc(); in select()
202 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in mustIssueImmediately()
212 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in dispatch()
241 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isReady()
H A DLSUnit.cpp70 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in dispatch()
89 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isAvailable()
98 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isReady()
156 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in onInstructionExecuted()
/freebsd-12.1/contrib/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.cpp52 if (LQResourceID && Inst.getDesc().MayLoad && in onEvent()
57 if (SQResourceID && Inst.getDesc().MayStore && in onEvent()
64 if (LQResourceID && Inst.getDesc().MayLoad) { in onEvent()
68 if (SQResourceID && Inst.getDesc().MayStore) { in onEvent()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCallIndirectFixup.cpp127 make_range(MI.operands_begin() + MI.getDesc().getNumDefs() + 1, in runOnMachineFunction()
130 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); in runOnMachineFunction()
133 while (MI.getNumOperands() > MI.getDesc().getNumDefs()) in runOnMachineFunction()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
H A DARMBaseInstrInfo.cpp150 uint64_t TSFlags = MI.getDesc().TSFlags; in convertToThreeAddress()
170 const MCInstrDesc &MCID = MI.getDesc(); in convertToThreeAddress()
706 const MCInstrDesc &MCID = MI.getDesc(); in getInstSizeInBytes()
2127 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
2387 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
3011 const MCInstrDesc &DefMCID = DefMI.getDesc(); in FoldImmediate()
3021 const MCInstrDesc &UseMCID = UseMI.getDesc(); in FoldImmediate()
3132 const MCInstrDesc &Desc = MI.getDesc(); in getNumMicroOpsSwiftLdSt()
3430 const MCInstrDesc &Desc = MI.getDesc(); in getNumMicroOps()
4405 const MCInstrDesc &MCID = MI.getDesc(); in getPredicationCost()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetSchedule.cpp111 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
136 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
199 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
328 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
H A DTargetInstrInfo.cpp151 const MCInstrDesc &MCID = MI.getDesc(); in commuteInstructionImpl()
188 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
193 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
283 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()
319 const MCInstrDesc &MCID = MI.getDesc(); in PredicateInstruction()
1065 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1099 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1109 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1121 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1122 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
H A DPeepholeOptimizer.cpp870 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1170 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1315 const MCInstrDesc &MCID = MI.getDesc(); in isLoadFoldable()
1335 const MCInstrDesc &MCID = MI.getDesc(); in isMoveImmediate()
1356 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) { in foldImmediate()
1520 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1758 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1833 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2049 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2050 Def->getDesc().isVariadic())) || in getNextSourceImpl()
H A DCriticalAntiDepBreaker.cpp195 if (i < MI.getDesc().getNumOperands()) in PrescanInstruction()
196 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in PrescanInstruction()
312 if (i < MI.getDesc().getNumOperands()) in ScanInstruction()
313 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF); in ScanInstruction()
H A DBreakFalseDeps.cpp127 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF); in pickBestRegisterForUndef()
193 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
/freebsd-12.1/contrib/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp54 const unsigned NumMicroOps = IR.getInstruction()->getDesc().NumMicroOps; in checkRCU()
90 const InstrDesc &Desc = IS.getDesc(); in dispatch()
167 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isAvailable()
H A DExecuteStage.cpp118 const InstrDesc &Desc = Inst.getDesc(); in verifyInstructionEliminated()
207 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in notifyReservedOrReleasedBuffers()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1515 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1604 if (!MI.getDesc().isPredicable()) in isPredicable()
1962 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
1972 !MI.getDesc().mayStore() && in isComplex()
1986 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2045 if (!ProdMI.getDesc().getNumDefs()) in isDependent()
2133 const MCInstrDesc &MID = MI.getDesc(); in isExtendable()
2156 const uint64_t F = MI.getDesc().TSFlags; in isExtended()
2954 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in hasNonExtEquivalent()
4199 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in getNonExtOpcode()
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H A DHexagonOptAddrMode.cpp127 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
194 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
357 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
416 const MCInstrDesc &MID = UseMI->getDesc(); in updateAddUses()
444 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
625 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
672 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/freebsd-12.1/contrib/llvm/lib/Support/
H A DStatistic.cpp147 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
197 Stats.Stats[i]->getDesc()); in PrintStatistics()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp568 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; in SafeInForbiddenSlot()
573 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; in HasForbiddenSlot()
580 return MI.getDesc().getSize(); in getInstSizeInBytes()
650 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
658 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands(); in genInstrWithNewOpc()
667 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
685 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp337 const MCInstrDesc &Desc = MI.getDesc(); in chooseBestLEA()
439 const MCInstrDesc &Desc = MI.getDesc(); in isReplaceable()
504 const MCInstrDesc &Desc = MI.getDesc(); in removeRedundantAddrCalc()
636 const MCInstrDesc &Desc = MI.getDesc(); in removeRedundantLEAs()

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