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/freebsd-12.1/contrib/bmake/unit-tests/
H A Ddotwait.mk5 TESTS= simple recursive shared cycle
58 cycle: cycle.1.99 .WAIT cycle.2.99
59 cycle.2.99: cycle.2.98 _ECHOUSE
60 cycle.2.98: cycle.2.97 _ECHOUSE
61 cycle.2.97: cycle.2.99 _ECHOUSE
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp118 int cycle = Stalls; in getHazardType() local
135 int StageCycle = cycle + (int)i; in getHazardType()
166 cycle += IS->getNextCycles(); in getHazardType()
185 unsigned cycle = 0; in EmitInstruction() local
194 assert(((cycle + i) < RequiredScoreboard.getDepth()) && in EmitInstruction()
201 freeUnits &= ~ReservedScoreboard[cycle + i]; in EmitInstruction()
205 freeUnits &= ~RequiredScoreboard[cycle + i]; in EmitInstruction()
217 RequiredScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
219 ReservedScoreboard[cycle + i] |= freeUnit; in EmitInstruction()
223 cycle += IS->getNextCycles(); in EmitInstruction()
/freebsd-12.1/usr.bin/gprof/
H A Dgprof.callg31 its membership in a cycle, if any.
58 parent's membership in a cycle, if any.
84 membership in a cycle, if any.
92 children) in the same cycle as the function. If
93 the function (or child) is a member of a cycle,
96 cycle as a whole.
103 cycle listings:
104 the cycle as a whole is listed with the same
106 the members of the cycle, and their contributions
107 to the time and call counts of the cycle.
H A Darcs.c360 int cycle; in cyclelink() local
388 cycle = 0; in cyclelink()
393 cycle += 1; in cyclelink()
394 cyclenlp = &cyclenl[cycle]; in cyclelink()
407 cyclenlp -> cycleno = cycle; /* internal number of cycle on */ in cyclelink()
416 printf( " is the head of cycle %d\n" , cycle ); in cyclelink()
423 memberp -> cycleno = cycle; in cyclelink()
435 if ( arcp -> arc_parentp -> cycleno == cycle ) { in cyclelink()
764 int cycle; in cycletime() local
768 for ( cycle = 1 ; cycle <= ncycle ; cycle += 1 ) { in cycletime()
[all …]
/freebsd-12.1/contrib/gcc/config/mips/
H A Dsb1.md8 ;; each cycle.
22 ;; insn can issue per cycle (fp1).
69 ;; For long cycle operations, the FPU has a 4 cycle pipeline that repeats,
71 ;; can have at most 4 long-cycle operations per pipe.
214 ;; store data), otherwise a latency of 1 cycle.
281 ;; mf{hi,lo} is 1 cycle.
318 ;; Blocks any other multiply insn issue for 1 cycle.
346 ;; cycle, and then deasserted on the latency cycle. So only one divide at
351 ;; cycle 7, and hi in cycle 8. All other insns write hi/lo regs in cycle 7.
392 ;; ??? madd/msub 4-cycle latency to itself (same fr?), but 8 cycle latency
[all …]
H A D4k.md79 ;; 4Kc/4Km MUL has 2 cycle latency, but has the special property that it will
80 ;; stall the integer unit pipeline. MUL 16x16 or 32x16 forces 1 cycle stall,
81 ;; while MUL 32x32 forces 2 cycle stall. If next insn use the result, an
115 ;; Move to HI/LO -> MADD/MSUB,MFHI/MFLO has a 1 cycle latency.
121 ;; Move from HI/LO -> integer operation has a 2 cycle latency.
/freebsd-12.1/contrib/ncurses/menu/
H A Dm_global.c389 bool cycle = (menu->opt & O_NONCYCLIC) ? FALSE : TRUE; in _nc_Link_Items() local
407 (cycle ? menu->items[(Last_in_Row >= Number_Of_Items) ? in _nc_Link_Items()
416 (cycle ? menu->items[row * Number_Of_Columns] : in _nc_Link_Items()
423 (cycle ? menu->items[(Last_in_Column >= Number_Of_Items) ? in _nc_Link_Items()
431 (cycle ? menu->items[(row + 1) < menu->rows ? in _nc_Link_Items()
455 (cycle ? (Last_in_Column >= Number_Of_Items) ? in _nc_Link_Items()
463 (cycle ? menu->items[row] : (ITEM *) 0); in _nc_Link_Items()
469 (cycle ? in _nc_Link_Items()
480 (cycle ? in _nc_Link_Items()
/freebsd-12.1/sys/contrib/octeon-sdk/
H A Dcvmx-clock.h111 uint64_t cycle; in cvmx_clock_get_count()
112 CVMX_RDHWR(cycle, 31); in cvmx_clock_get_count()
113 return(cycle); in cvmx_clock_get_count()
H A Dcvmx-log.c85 uint64_t cycle :53; /* Low bits of the cycle counter as a timestamp */ member
185 header.s.cycle = cvmx_get_cycle(); in __cvmx_log_build_header()
476 if (header.s.cycle == 0) in cvmx_log_display()
478 printf("%llu: ", (unsigned long long)header.s.cycle); in cvmx_log_display()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td47 // Each LSU pipeline can complete a load or store in one cycle.
52 // FX loads have a two cycle load-to-use latency (so one "bubble" cycle).
53 // VSU loads have a three cycle load-to-use latency (so two "bubble" cycle).
55 // Frequent FX ops. take only one cycle and results can be used again in the
56 // next cycle (there is a self-bypass). Getting results from the other FX
57 // pipeline takes an additional cycle.
62 // (either to a float or XC op). prevents dispatch in that cycle to VS2 of any
70 // share the same write-back, and have a 5-cycle latency difference, so the
388 let IssueWidth = 6; // 4 (non-branch) instructions are dispatched per cycle.
391 // cycle (from all queues) is 8.
H A DPPCScheduleP9.td151 // However, the ALU unit is only every busy for 1 cycle at a time and may
152 // receive new instructions each cycle.
297 // Three cycle permute operations.
304 // Stores are listed as having a single cycle of latency. This is not
305 // completely accurate since it takes more than 1 cycle to actually store
307 // considered complete after one cycle.
357 // 2 or 5 cycle latencies for the branch unit.
366 // 6 cycle latency for the crypto unit
/freebsd-12.1/contrib/gcc/config/arm/
H A Darm1020e.md81 ;; the shift value in a second cycle. Pretend we take two cycles in
132 ;; cycle in which both words are available.
135 ;; three iterations through the execute cycle, and make their results
136 ;; available after the memory cycle.
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
185 ;; base address is 64-bit aligned; if it is not, an additional cycle
187 ;; aligned. Because the processor can load two registers per cycle,
366 ;; Arithmetic to other arithmetic saves a cycle due to forwarding
386 ;; - After a store: one extra cycle for both fsts and fstd
[all …]
H A Darm1026ejs.md81 ;; the shift value in a second cycle. Pretend we take two cycles in
132 ;; cycle in which both words are available.
135 ;; three iterations through the execute cycle, and make their results
136 ;; available after the memory cycle.
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
165 ;; with LSL of zero. The remainder take 1 cycle to execute.
185 ;; base address is 64-bit aligned; if it is not, an additional cycle
187 ;; aligned. Because the processor can load two registers per cycle,
/freebsd-12.1/sys/gnu/dts/arm/
H A Domap3430-sdp.dts76 gpmc,rd-cycle-ns = <186>;
77 gpmc,wr-cycle-ns = <186>;
126 gpmc,rd-cycle-ns = <72>;
127 gpmc,wr-cycle-ns = <72>;
172 gpmc,rd-cycle-ns = <108>;
173 gpmc,wr-cycle-ns = <96>;
/freebsd-12.1/contrib/gcc/
H A Dgcov.c102 unsigned int cycle : 1; member
1524 block->u.cycle.arc = NULL; in add_line_counts()
1525 block->u.cycle.ident = ~0U; in add_line_counts()
1655 arc->cycle in accumulate_line_counts()
1659 || dst->u.cycle.arc) in accumulate_line_counts()
1682 cycle_arc->cycle = 1; in accumulate_line_counts()
1693 arc = head->u.cycle.arc; in accumulate_line_counts()
1694 head->u.cycle.arc = NULL; in accumulate_line_counts()
1703 dst->u.cycle.arc = arc; in accumulate_line_counts()
1709 arc = head->u.cycle.arc; in accumulate_line_counts()
[all …]
/freebsd-12.1/sys/dev/pwm/
H A Dpwmbus_if.m52 # Config the period (Total number of cycle in ns) and
53 # the duty (active number of cycle in ns)
63 # Get the period (Total number of cycle in ns) and
64 # the duty (active number of cycle in ns)
/freebsd-12.1/contrib/gdb/gdb/
H A Dvalprint.c605 int cycle; in print_octal_chars() local
640 cycle = (len * BITS_IN_BYTES) % BITS_IN_OCTAL; in print_octal_chars()
650 switch (cycle) in print_octal_chars()
690 cycle++; in print_octal_chars()
691 cycle = cycle % BITS_IN_OCTAL; in print_octal_chars()
700 switch (cycle) in print_octal_chars()
737 cycle++; in print_octal_chars()
738 cycle = cycle % BITS_IN_OCTAL; in print_octal_chars()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleA8.td96 // Result written in E5, but that is relative to the last cycle of multicycle,
125 // FIXME: lsl by 2 takes 1 cycle.
152 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
230 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
394 // FIXME: A8_LSPipe cycle time is dynamic, this assumes 3 to 4 registers.
860 // Quad-register Permute (3 cycle issue)
930 // Double-register Integer Binary (4 cycle)
934 // Quad-register Integer Binary (4 cycle)
963 // Double-register Integer Shift (4 cycle)
967 // Quad-register Integer Shift (4 cycle)
[all …]
/freebsd-12.1/lib/libthr/thread/
H A Dthr_barrier.c138 int64_t cycle; in _pthread_barrier_wait() local
161 cycle = bar->b_cycle; in _pthread_barrier_wait()
167 } while (cycle == bar->b_cycle); in _pthread_barrier_wait()
H A Dthr_resume_np.c97 thread->cycle++; in resume_common()
98 _thr_umtx_wake(&thread->cycle, 1, 0); in resume_common()
H A Dthr_sig.c356 uint32_t cycle; in check_suspend() local
380 curthread->cycle++; in check_suspend()
381 cycle = curthread->cycle; in check_suspend()
384 _thr_umtx_wake(&curthread->cycle, INT_MAX, 0); in check_suspend()
394 _thr_umtx_wait_uint(&curthread->cycle, cycle, NULL, 0); in check_suspend()
/freebsd-12.1/usr.sbin/fwcontrol/
H A Dfwdv.c265 int system=-1, pad_acc, cycle_acc, cycle, f_cycle, f_frac; in dvsend() local
356 cycle = 1; in dvsend()
357 cycle_acc = frame_cycle[system].d * cycle; in dvsend()
372 ciph->fdf.dv.cyc = htons(cycle << 12 | f_frac); in dvsend()
389 cycle ++; in dvsend()
397 cycle ++; in dvsend()
/freebsd-12.1/sys/gnu/dts/arm64/broadcom/stingray/
H A Dstingray-board-base.dtsi38 full-pwr-cycle;
42 full-pwr-cycle;
/freebsd-12.1/sys/powerpc/powermac/
H A Data_macio.c86 int cycle; /* minimum cycle time [ns] */ member
271 min_cycle = udma_timings[mode & ATA_MODE_MASK].cycle; in ata_macio_setmode()
281 min_cycle = dma_timings[mode & ATA_MODE_MASK].cycle; in ata_macio_setmode()
304 pio_timings[(mode & ATA_MODE_MASK) - ATA_PIO0].cycle; in ata_macio_setmode()
/freebsd-12.1/contrib/gcc/config/sparc/
H A Dultra3.md59 ;; ??? It can run from 6 to 9 cycles. The first cycle the MS pipe
83 (eq_attr "us3load_type" "2cycle")))
89 (eq_attr "us3load_type" "3cycle")))
164 ;; An integer branch may execute in the same cycle as the compare
168 ;; If FMOVfcc is user of FPCMP, latency is only 1 cycle.

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