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Searched refs:cacheline_size (Results 1 – 13 of 13) sorted by relevance

/freebsd-12.1/stand/libsa/powerpc/
H A Dsyncicache.c51 int cacheline_size = 32; variable
57 int cacheline_size = 0; variable
67 clen = sizeof(cacheline_size); in getcachelinesize()
70 &cacheline_size, &clen, NULL, 0) < 0 || !cacheline_size) { in getcachelinesize()
83 if (!cacheline_size) in __syncicache()
87 off = (u_int)from & (cacheline_size - 1); in __syncicache()
93 p += cacheline_size; in __syncicache()
94 } while ((l -= cacheline_size) > 0); in __syncicache()
99 p += cacheline_size; in __syncicache()
100 } while ((len -= cacheline_size) > 0); in __syncicache()
/freebsd-12.1/lib/libc/powerpc/gen/
H A Dsyncicache.c53 int cacheline_size = 32; variable
59 int cacheline_size = 0; variable
69 clen = sizeof(cacheline_size); in getcachelinesize()
71 if (sysctl(cachemib, nitems(cachemib), &cacheline_size, &clen, in getcachelinesize()
72 NULL, 0) < 0 || !cacheline_size) { in getcachelinesize()
85 if (!cacheline_size) in __syncicache()
89 off = (u_int)from & (cacheline_size - 1); in __syncicache()
95 p += cacheline_size; in __syncicache()
96 } while ((l -= cacheline_size) > 0); in __syncicache()
101 p += cacheline_size; in __syncicache()
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/freebsd-12.1/lib/libc/powerpc64/gen/
H A Dsyncicache.c53 int cacheline_size = 32; variable
59 int cacheline_size = 0; variable
69 clen = sizeof(cacheline_size); in getcachelinesize()
71 if (sysctl(cachemib, nitems(cachemib), &cacheline_size, &clen, in getcachelinesize()
72 NULL, 0) < 0 || !cacheline_size) { in getcachelinesize()
85 if (!cacheline_size) in __syncicache()
89 off = (uintptr_t)from & (cacheline_size - 1); in __syncicache()
95 p += cacheline_size; in __syncicache()
96 } while ((l -= cacheline_size) > 0); in __syncicache()
101 p += cacheline_size; in __syncicache()
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/freebsd-12.1/sys/powerpc/powerpc/
H A Dsyncicache.c56 off = (uintptr_t)from & (cacheline_size - 1); in __syncicache()
62 p += cacheline_size; in __syncicache()
63 } while ((l -= cacheline_size) > 0); in __syncicache()
68 p += cacheline_size; in __syncicache()
69 } while ((len -= cacheline_size) > 0); in __syncicache()
H A Dmachdep.c134 int cacheline_size = 128; variable
136 int cacheline_size = 32; variable
157 SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
158 CTLFLAG_RD, &cacheline_size, 0, "");
466 off = addr & (cacheline_size - 1); in cpu_flush_dcache()
468 len = roundup2(len + off, cacheline_size); in cpu_flush_dcache()
473 addr += cacheline_size; in cpu_flush_dcache()
474 len -= cacheline_size; in cpu_flush_dcache()
553 __syncicache(__DEVOLATILE(uint32_t *, p), cacheline_size); in DB_SHOW_COMMAND()
/freebsd-12.1/sys/powerpc/aim/
H A Daim_machdep.c285 for (cacheline_size = 0; cacheline_size < 0x100; cacheline_size++) in aim_cpu_init()
286 cache_check[cacheline_size] = 0xff; in aim_cpu_init()
291 for (cacheline_size = 0; cacheline_size < 0x100 && in aim_cpu_init()
292 cache_check[cacheline_size] == 0; cacheline_size++); in aim_cpu_init()
295 if (cacheline_size == 0) { in aim_cpu_init()
297 cacheline_size = 32; in aim_cpu_init()
H A Dmmu_oea.c1080 for (off = 0; off < PAGE_SIZE; off += cacheline_size) in moea_zero_page()
H A Dmmu_oea64.c1298 for (off = 0; off < PAGE_SIZE; off += cacheline_size) in moea64_zero_page()
/freebsd-12.1/sys/powerpc/include/
H A Dmd_var.h53 extern int cacheline_size;
/freebsd-12.1/sys/powerpc/booke/
H A Dbooke_machdep.c364 cacheline_size = 64; in booke_init()
383 #define RES_GRANULE cacheline_size
H A Dpmap.c3002 for (off = 0; off < PAGE_SIZE; off += cacheline_size) in mmu_booke_zero_page()
3010 for (off = 0; off < PAGE_SIZE; off += cacheline_size) in mmu_booke_zero_page()
/freebsd-12.1/sys/dev/drm2/i915/
H A Dintel_pm.c1116 entries = DIV_ROUND_UP(entries, display->cacheline_size); in g4x_compute_wm0()
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; in g4x_compute_wm0()
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_wm0()
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in g4x_compute_srwm()
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_srwm()
1440 i965_cursor_wm_info.cacheline_size); in i965_update_wm()
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); in i9xx_update_wm()
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in ironlake_compute_srwm()
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in ironlake_compute_srwm()
2067 tlb_miss = display->fifo_size*display->cacheline_size - in sandybridge_compute_sprite_wm()
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H A Dintel_drv.h285 unsigned long cacheline_size; member