Lines Matching refs:cacheline_size
985 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); in intel_calculate_wm()
1113 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; in g4x_compute_wm0()
1116 entries = DIV_ROUND_UP(entries, display->cacheline_size); in g4x_compute_wm0()
1125 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; in g4x_compute_wm0()
1128 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_wm0()
1204 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in g4x_compute_srwm()
1209 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in g4x_compute_srwm()
1440 i965_cursor_wm_info.cacheline_size); in i965_update_wm()
1548 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); in i9xx_update_wm()
1694 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in ironlake_compute_srwm()
1705 entries = DIV_ROUND_UP(entries, cursor->cacheline_size); in ironlake_compute_srwm()
2067 tlb_miss = display->fifo_size*display->cacheline_size - in sandybridge_compute_sprite_wm()
2071 entries = DIV_ROUND_UP(entries, display->cacheline_size); in sandybridge_compute_sprite_wm()
2117 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); in sandybridge_compute_sprite_srwm()