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Searched refs:ZeroReg (Results 1 – 22 of 22) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp164 unsigned ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
169 ZeroReg); in runOnMachineFunction()
175 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FlagsCopyLowering.cpp991 unsigned ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCarryExtended() local
992 BuildMI(MBB, SetPos, SetLoc, TII->get(X86::MOV32r0), ZeroReg); in rewriteSetCarryExtended()
993 ZeroReg = AdjustReg(ZeroReg); in rewriteSetCarryExtended()
1018 .addReg(ZeroReg) in rewriteSetCarryExtended()
H A DX86FrameLowering.cpp590 ZeroReg = InProlog ? (unsigned)X86::RCX in emitStackProbeInline() local
650 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInline()
651 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInline()
652 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInline()
659 .addReg(ZeroReg); in emitStackProbeInline()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp88 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
96 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
152 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
183 if (ZeroReg) in copyPhysReg()
184 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp95 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
103 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
109 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
129 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
132 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp143 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
144 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3080 Register ZeroReg, RegisterOperand GPROpnd> {
3087 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
3089 (Addiu ZeroReg, tblockaddress:$in)>;
3090 def : MipsPat<(MipsLo tjumptable:$in), (Addiu ZeroReg, tjumptable:$in)>;
3091 def : MipsPat<(MipsLo tconstpool:$in), (Addiu ZeroReg, tconstpool:$in)>;
3093 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3094 def : MipsPat<(MipsLo texternalsym:$in), (Addiu ZeroReg, texternalsym:$in)>;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp2314 MIB.addReg(ZeroReg); in copyGPRRegTuple()
4162 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4169 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4185 .addReg(ZeroReg) in genAlternativeCodeSequence()
4201 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
4205 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4211 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
4219 .addReg(ZeroReg) in genAlternativeCodeSequence()
4254 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
4261 ZeroReg = AArch64::XZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64ExpandPseudoInsts.cpp77 unsigned ExtendImm, unsigned ZeroReg,
591 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
624 BuildMI(LoadCmpBB, DL, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64InstrInfo.h127 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64ISelDAGToDAG.cpp2496 unsigned ZeroReg; in tryShiftAmountMod() local
2500 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
2504 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
2507 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp391 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
394 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4921 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4924 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true, in selectSDiv()
H A DAArch64ISelLowering.cpp10193 unsigned ZeroReg; in replaceZeroVectorStore() local
10196 ZeroReg = AArch64::WZR; in replaceZeroVectorStore()
10199 ZeroReg = AArch64::XZR; in replaceZeroVectorStore()
10203 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT); in replaceZeroVectorStore()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp498 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
499 putConstant(I, ZeroReg, 0); in selectCmp()
504 ZeroReg)) in selectCmp()
510 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1500 unsigned ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1503 .addReg(ZeroReg).addImm(1) in SelectCmp()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h701 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
705 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
711 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2676 SrcReg = ZeroReg; in loadImmediate()
3952 unsigned ZeroReg; in expandDivRem() local
3957 ZeroReg = Mips::ZERO_64; in expandDivRem()
3961 ZeroReg = Mips::ZERO; in expandDivRem()
3985 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
3992 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
3998 TOut.emitRRR(SubOp, RdReg, ZeroReg, RsReg, IDLoc, STI); in expandDivRem()
4017 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4037 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4065 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI); in expandDivRem()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1359 unsigned ZeroReg; in FoldImmediate() local
1362 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in FoldImmediate()
1364 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in FoldImmediate()
1369 UseMI.getOperand(UseIdx).setReg(ZeroReg); in FoldImmediate()
H A DPPCISelLowering.cpp9923 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitPartwordAtomicBinary() local
9992 if (ptrA != ZeroReg) { in EmitPartwordAtomicBinary()
10037 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
10081 .addReg(ZeroReg) in EmitPartwordAtomicBinary()
10783 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO; in EmitInstrWithCustomInserter() local
10816 if (ptrA != ZeroReg) { in EmitInstrWithCustomInserter()
10873 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
10897 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
10910 .addReg(ZeroReg) in EmitInstrWithCustomInserter()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DIRTranslator.cpp1638 unsigned ZeroReg = getOrCreateVReg(*ZeroVal); in translate() local
1639 EntryBuilder->buildCast(Reg, ZeroReg); in translate()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5384 unsigned ZeroReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); in convertNonUniformLoopRegion() local
5386 ZeroReg, 0); in convertNonUniformLoopRegion()
5387 HeaderPHIBuilder.addReg(ZeroReg); in convertNonUniformLoopRegion()