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Searched refs:Ws (Results 1 – 3 of 3) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp2632 SDValue Ws; in lowerVECTOR_SHUFFLE_ILVEV() local
2648 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVEV()
2650 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVEV()
2678 SDValue Ws; in lowerVECTOR_SHUFFLE_ILVOD() local
2694 Ws = Op->getOperand(0); in lowerVECTOR_SHUFFLE_ILVOD()
2696 Ws = Op->getOperand(1); in lowerVECTOR_SHUFFLE_ILVOD()
2725 SDValue Ws; in lowerVECTOR_SHUFFLE_ILVR() local
2773 SDValue Ws; in lowerVECTOR_SHUFFLE_ILVL() local
2820 SDValue Ws; in lowerVECTOR_SHUFFLE_PCKEV() local
2863 SDValue Ws; in lowerVECTOR_SHUFFLE_PCKOD() local
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp299 uint16_t I = Odd, Ws = Rs.width(); in evaluate() local
300 assert(Ws == Rt.width()); in evaluate()
303 while (I*BW < Ws) { in evaluate()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td3971 bits<5> Ws;
3974 let Inst{20-16} = Ws;
3978 let Constraints = "@earlyclobber $Ws";
3985 (outs GPR32:$Ws),
3989 bits<5> Ws;
3993 let Inst{20-16} = Ws;
3998 let Constraints = "@earlyclobber $Ws";
10387 // CAS{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
10391 // SWP{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
10393 // LD<OP>{<order>}[<size>] <Ws>, <Wt>, [<Xn|SP>]
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