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Searched refs:WriteSequence (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td376 def P9_LoadAndALUOp_6C : WriteSequence<[P9_LS_4C, P9_ALU_2C]>;
377 def P9_LoadAndALUOp_7C : WriteSequence<[P9_LS_5C, P9_ALU_2C]>;
378 def P9_LoadAndALU2Op_7C : WriteSequence<[P9_LS_4C, P9_ALU_3C]>;
379 def P9_LoadAndALU2Op_8C : WriteSequence<[P9_LS_5C, P9_ALU_3C]>;
380 def P9_LoadAndPMOp_8C : WriteSequence<[P9_LS_5C, P9_PM_3C]>;
381 def P9_LoadAndLoadOp_8C : WriteSequence<[P9_LS_4C, P9_LS_4C]>;
385 def P9_StoreAndALUOp_3C : WriteSequence<[P9_LS_1C, P9_ALU_2C]>;
390 WriteSequence<[P9_ALU_2C, P9_ALU_2C, P9_ALU_2C]>;
391 def P9_DPOpAndALUOp_7C : WriteSequence<[P9_DP_5C, P9_ALU_2C]>;
392 def P9_DPOpAndALUOp_9C : WriteSequence<[P9_DP_7C, P9_ALU_2C]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td55 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
59 def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;
66 def WriteSTX : WriteSequence<[WriteST, WriteLD]>;
90 def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>;
91 def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
94 def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
95 def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;
H A DAArch64SchedExynosM1.td359 def M1WriteVSTA : WriteSequence<[WriteVST], 2>;
360 def M1WriteVSTB : WriteSequence<[WriteVST], 3>;
361 def M1WriteVSTC : WriteSequence<[WriteVST], 4>;
590 def : InstRW<[WriteSequence<[M1WriteNAL11], 2>],
592 def : InstRW<[WriteSequence<[M1WriteNAL11], 3>],
594 def : InstRW<[WriteSequence<[M1WriteNAL11], 4>],
597 def : InstRW<[WriteSequence<[M1WriteNAL12], 2>],
599 def : InstRW<[WriteSequence<[M1WriteNAL12], 3>],
601 def : InstRW<[WriteSequence<[M1WriteNAL12], 4>],
H A DAArch64SchedCyclone.td356 def CyWriteCopyToFPR : WriteSequence<[WriteVLD, WriteV]>;
360 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
580 def CyWriteCvtToFPR : WriteSequence<[WriteVLD, CyWriteV4]>;
584 def CyWriteCvtToGPR : WriteSequence<[CyWriteV6, WriteLD]>;
H A DAArch64SchedExynosM3.td410 def M3WriteVSTA : WriteSequence<[WriteVST], 2>;
411 def M3WriteVSTB : WriteSequence<[WriteVST], 3>;
412 def M3WriteVSTC : WriteSequence<[WriteVST], 4>;
H A DAArch64SchedExynosM4.td418 def M4WriteVSTA : WriteSequence<[WriteVST], 2>;
419 def M4WriteVSTB : WriteSequence<[WriteVST], 3>;
420 def M4WriteVSTC : WriteSequence<[WriteVST], 4>;
H A DAArch64SchedFalkorDetails.td1238 def : InstRW<[WriteSequence<[FalkorWr_1XYZ_1cyc, FalkorWr_1XYZ_1cyc]>],
1240 def : InstRW<[WriteSequence<[FalkorWr_1LD_3cyc, FalkorWr_1XYZ_1cyc]>],
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td81 def SwiftWriteP01OneCycle2x : WriteSequence<[SwiftWriteP01OneCycle], 2>;
82 def SwiftWriteP01OneCycle3x : WriteSequence<[SwiftWriteP01OneCycle], 3>;
106 def SwiftWrite#Num#xP2 : WriteSequence<[SwiftWriteP2], Num>;
108 def SwiftWriteP01OneCycle2x_load : WriteSequence<[SwiftWriteP01OneCycle,
174 def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
632 def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
635 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
638 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
643 def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>,
644 WriteSequence<[SwiftWrite1Cycle, SwiftWriteP2FourCycle,
[all …]
H A DARMScheduleA9.td1882 class A9WriteLMOpsListType<list<WriteSequence> writes> {
1883 list <WriteSequence> Writes = writes;
2048 def A9WriteAdr#NumAddr : WriteSequence<[A9WriteAdr], NumAddr>;
2086 def A9WriteL#NumAddr : WriteSequence<
2088 def A9WriteL#NumAddr#Hi : WriteSequence<
2151 def A9WriteLfp#NumAddr : WriteSequence<
2156 def A9WriteLfp#NumAddr#Mov : WriteSequence<
2186 def A9WriteLMfp#NumAddr : WriteSequence<
2191 def A9WriteLMfp#NumAddr#Hi : WriteSequence<
2258 def A9WriteI2 : WriteSequence<[A9WriteI, A9WriteI]>;
[all …]
H A DARMScheduleA57.td258 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_1cyc_1I]>;
260 WriteSequence<[A57Write_1cyc_1I, A57Write_1cyc_1I, A57Write_4cyc_1L]>;
H A DARMScheduleR52.td458 def R52WriteISTM#NumAddr : WriteSequence<[R52WriteIStIncAddr], NumAddr>;
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td512 // FIXME: This isn't quite right since the implementation of WriteSequence
515 def P5600WriteMoveGPRToFPU : WriteSequence<[P5600WriteMoveGPRToOtherUnits,
518 // FIXME: This isn't quite right since the implementation of WriteSequence
521 def P5600WriteMoveFPUToGPR : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
524 // FIXME: This isn't quite right since the implementation of WriteSequence
527 def P5600WriteStoreFPUS : WriteSequence<[P5600WriteMoveFPUSToOtherUnits,
530 // FIXME: This isn't quite right since the implementation of WriteSequence
533 def P5600WriteStoreFPUL : WriteSequence<[P5600WriteMoveFPULToOtherUnits,
536 // FIXME: This isn't quite right since the implementation of WriteSequence
539 def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits,
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td30 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86Schedule.td117 def WriteCopy : WriteSequence<[WriteLoad, WriteStore]>; // mem->mem copy
122 def WriteALURMW : WriteSequence<[WriteALULd, WriteRMW]>;
123 def WriteADCRMW : WriteSequence<[WriteADCLd, WriteRMW]>;
174 def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;
175 def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSchedule.td244 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
297 // by defining a WriteSequence, or simply listing extra writes in the
448 // SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or
/freebsd-12.1/sys/dev/mps/mpi/
H A Dmpi2.h165 U32 WriteSequence; /* 0x04 */ member
H A Dmpi2_history.txt80 * Added a sixth key value for the WriteSequence register
/freebsd-12.1/sys/dev/mpr/mpi/
H A Dmpi2.h237 U32 WriteSequence; /* 0x04 */ member
H A Dmpi2_history.txt81 * Added a sixth key value for the WriteSequence register