| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2865 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2901 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2938 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2946 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2957 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2965 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2975 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3011 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
3200 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3208 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
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| H A D | ARMInstrFormats.td | 2110 bits<5> Vd;
2180 bits<5> Vd;
2206 bits<5> Vd;
2221 bits<5> Vd;
2259 bits<5> Vd;
2281 bits<5> Vd;
2313 bits<5> Vd;
2330 bits<5> Vd;
2358 bits<5> Vd;
2379 bits<5> Vd;
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| H A D | ARMInstrVFP.td | 1628 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1639 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
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| /freebsd-12.1/tests/sys/cddl/zfs/tests/acl/nontrivial/ |
| H A D | zfs_acl_chmod_inherit_003_pos.ksh | 297 $LS -Vd $basedir
298 $LS -Vd $node
314 $LS -Vd $basedir
315 $LS -Vd $node
339 $LS -Vd $basedir
340 $LS -Vd $node
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| /freebsd-12.1/contrib/llvm/tools/clang/include/clang/Analysis/Analyses/ |
| H A D | ThreadSafetyTIL.h | 381 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
382 Flags = Vd.kind(); in Variable()
665 Function(Variable *Vd, SExpr *Bd) in Function() argument
667 Vd->setKind(Variable::VK_Fun); in Function()
672 Vd->setKind(Variable::VK_Fun); in Function()
716 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
719 Vd->setKind(Variable::VK_SFun); in SFunction()
720 Vd->Definition = this; in SFunction()
727 Vd->Definition = this; in SFunction()
1858 Let(Variable *Vd, SExpr *Bd) : SExpr(COP_Let), VarDecl(Vd), Body(Bd) { in Let() argument
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/Analysis/ |
| H A D | ThreadSafety.cpp | 263 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
295 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
301 void checkBeforeAfter(const ValueDecl* Vd,
1083 for (const auto *At : Vd->attrs()) { in insertAttrExprs()
1111 ArgInfo->Vect.push_back(Vd); in insertAttrExprs()
1127 auto It = BMap.find(Vd); in getBeforeInfoForDecl()
1130 Info = insertAttrExprs(Vd, Analyzer); in getBeforeInfoForDecl()
1147 if (!Vd) in checkBeforeAfter()
1172 if (CycMap.find(Vd) == CycMap.end()) { in checkBeforeAfter()
1173 CycMap.insert(std::make_pair(Vd, true)); in checkBeforeAfter()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 3391 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
3393 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
4956 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4957 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4958 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4959 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
4961 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
4962 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
4963 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
4964 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
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| H A D | AArch64InstrFormats.td | 7028 bits<5> Vd;
7040 let Inst{4-0} = Vd;
7047 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
7049 bits<5> Vd;
7061 let Inst{4-0} = Vd;
10276 bits<5> Vd;
10280 let Inst{4-0} = Vd;
10314 "{\t$Vd.2d, $Vn.2d, $Vm.2d}", "$Vd = $Vdst">;
10320 "{\t$Vd.4s, $Vn.4s, $Vm.4s}", "$Vd = $Vdst">;
10323 asm, "{\t$Vd, $Vn, $Vm.2d}", "$Vd = $Vdst">;
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| H A D | AArch64SchedPredicates.td | 340 [// MOVI Vd, #0
345 // MOVI Vd, #0, LSL #0
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| H A D | AArch64SchedCyclone.td | 323 // FMOVv2f64ns Vd.2d, #0.0
332 // ORR.16b Vd,Vn,Vn
633 // Vd is read 5 cycles after issuing the vector load.
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| H A D | SVEInstrFormats.td | 2277 asm, "\t$Vd, $Pg, $Zn",
2281 bits<5> Vd;
2290 let Inst{4-0} = Vd;
3256 : I<(outs dstRegtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
3257 asm, "\t$Vd, $Pg, $Zn",
3261 bits<5> Vd;
3270 let Inst{4-0} = Vd;
4283 : I<(outs regtype:$Vd), (ins PPR3bAny:$Pg, zprty:$Zn),
4284 asm, "\t$Vd, $Pg, $Zn",
4288 bits<5> Vd;
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1248 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1252 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1253 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1272 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1276 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1277 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
5120 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTD() local
5121 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTD()
5179 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); in DecodeVCVTQ() local
5180 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); in DecodeVCVTQ()
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| /freebsd-12.1/tests/sys/cddl/zfs/tests/acl/ |
| H A D | acl_common.kshlib | 85 $LS -Vd $obj | $NAWK '(NR != 1) {print $0}'
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1156 unsigned Vd = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1157 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd) in expandPostRAPseudo()
1158 .addReg(Vd, RegState::Undef) in expandPostRAPseudo()
1159 .addReg(Vd, RegState::Undef); in expandPostRAPseudo()
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| H A D | HexagonPseudo.td | 465 def PS_vdd0: InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
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| /freebsd-12.1/contrib/llvm/tools/llvm-objdump/ |
| H A D | MachODump.cpp | 9703 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
9704 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()
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