1248   unsigned Vd = fieldFromInstruction(Val, 8, 5);  in DecodeSPRRegListOperand()  local
1252   if (regs == 0 || (Vd + regs) > 32) {  in DecodeSPRRegListOperand()
1253     regs = Vd + regs > 32 ? 32 - Vd : regs;  in DecodeSPRRegListOperand()
1258   if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeSPRRegListOperand()
1261     if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))  in DecodeSPRRegListOperand()
1272   unsigned Vd = fieldFromInstruction(Val, 8, 5);  in DecodeDPRRegListOperand()  local
1276   if (regs == 0 || regs > 16 || (Vd + regs) > 32) {  in DecodeDPRRegListOperand()
1277     regs = Vd + regs > 32 ? 32 - Vd : regs;  in DecodeDPRRegListOperand()
1283   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeDPRRegListOperand()
1286     if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))  in DecodeDPRRegListOperand()
5120   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeVCVTD()  local
5121   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeVCVTD()
5164   if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeVCVTD()
5179   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeVCVTQ()  local
5180   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeVCVTQ()
5223   if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))  in DecodeVCVTQ()
5236   unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);  in DecodeNEONComplexLane64Instruction()  local
5237   Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);  in DecodeNEONComplexLane64Instruction()
5249   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))  in DecodeNEONComplexLane64Instruction()
5251   if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))  in DecodeNEONComplexLane64Instruction()