| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 745 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
844 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
2229 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
2231 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
2233 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
2245 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
2322 unsigned TrueReg = TRI->lookThruCopyLike(Reg, MRI); in getForwardingDefMI() local
2323 if (TargetRegisterInfo::isVirtualRegister(TrueReg)) { in getForwardingDefMI()
2324 DefMI = MRI->getVRegDef(TrueReg); in getForwardingDefMI()
[all …]
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| H A D | PPCMIPeephole.cpp | 402 unsigned TrueReg = in simplifyCode() local
404 if (!TargetRegisterInfo::isVirtualRegister(TrueReg)) in simplifyCode()
406 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
465 unsigned TrueReg = in simplifyCode() local
467 if (!TargetRegisterInfo::isVirtualRegister(TrueReg)) in simplifyCode()
469 MachineInstr *DefMI = MRI->getVRegDef(TrueReg); in simplifyCode()
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| H A D | PPCInstrInfo.h | 284 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 697 auto TrueReg = MIB->getOperand(2).getReg(); in selectSelect() local
699 assert(validOpRegPair(MRI, ResReg, TrueReg, 32, ARM::GPRRegBankID) && in selectSelect()
700 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
704 .addUse(TrueReg) in selectSelect()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 562 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
574 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
597 unsigned TrueReg, in insertSelect() argument
615 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg); in insertSelect()
617 TrueReg = TReg; in insertSelect()
626 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
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| H A D | SystemZInstrInfo.h | 215 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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| H A D | SystemZISelLowering.cpp | 6259 unsigned TrueReg = MIIt->getOperand(1).getReg(); in createPHIsForSelects() local
6266 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
6268 if (RegRewriteTable.find(TrueReg) != RegRewriteTable.end()) in createPHIsForSelects()
6269 TrueReg = RegRewriteTable[TrueReg].first; in createPHIsForSelects()
6275 .addReg(TrueReg).addMBB(TrueMBB) in createPHIsForSelects()
6279 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.h | 279 unsigned TrueReg, unsigned FalseReg,
286 unsigned TrueReg, unsigned FalseReg) const override;
291 unsigned TrueReg, unsigned FalseReg) const;
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| H A D | SIInstrInfo.cpp | 708 .addReg(TrueReg) in insertVectorSelect()
720 .addReg(TrueReg) in insertVectorSelect()
731 .addReg(TrueReg) in insertVectorSelect()
743 .addReg(TrueReg) in insertVectorSelect()
754 .addReg(TrueReg) in insertVectorSelect()
769 .addReg(TrueReg) in insertVectorSelect()
783 .addReg(TrueReg) in insertVectorSelect()
1860 std::swap(TrueReg, FalseReg); in insertSelect()
1875 .addReg(TrueReg); in insertSelect()
1885 .addReg(TrueReg); in insertSelect()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 880 unsigned TrueReg = getRegForValue(Select->getTrueValue()); in selectSelect() local
881 if (TrueReg == 0) in selectSelect()
889 std::swap(TrueReg, FalseReg); in selectSelect()
923 .addReg(TrueReg) in selectSelect()
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| H A D | WebAssemblyISelLowering.cpp | 348 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
354 TrueReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
388 BuildMI(TrueMBB, DL, TII.get(IConst), TrueReg).addImm(Substitute); in LowerFPToInt()
392 .addReg(TrueReg) in LowerFPToInt()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 758 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in canInsertSelect() argument
782 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.h | 178 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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| H A D | AArch64InstrInfo.cpp | 497 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
503 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
517 if (canFoldIntoCSel(MRI, TrueReg)) in canInsertSelect()
541 unsigned TrueReg, unsigned FalseReg) const { in insertSelect() argument
644 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg); in insertSelect()
649 TrueReg = FalseReg; in insertSelect()
663 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
668 .addReg(TrueReg) in insertSelect()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.h | 347 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
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| H A D | X86InstrInfo.cpp | 2875 unsigned TrueReg, unsigned FalseReg, in canInsertSelect() argument
2889 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
2912 ArrayRef<MachineOperand> Cond, unsigned TrueReg, in insertSelect() argument
2921 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg); in insertSelect()
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