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Searched refs:SubRegIndex (Results 1 – 25 of 31) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp223 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
224 Src0 = TRI.getSubReg(Src0, SubRegIndex); in runOnMachineFunction()
225 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
238 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() local
239 DstReg = TRI.getSubReg(DstReg, SubRegIndex); in runOnMachineFunction()
H A DAMDGPURegisterInfo.td17 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
H A DSIRegisterInfo.td15 list<SubRegIndex> ret2 = [sub0, sub1];
16 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
17 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
18 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
19 list<SubRegIndex> ret16 = [sub0, sub1, sub2, sub3,
24 list<SubRegIndex> ret = !if(!eq(size, 2), ret2,
263 list<SubRegIndex> indices = getSubRegs<size>.ret,
H A DSIInstructions.td738 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
741 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index)
745 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
748 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index)
754 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
757 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index)
761 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
764 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index)
770 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
773 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index)
[all …]
H A DR600.td25 def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
H A DR600InstrInfo.cpp81 unsigned SubRegIndex = AMDGPURegisterInfo::getSubRegFromChannel(I); in copyPhysReg() local
83 RI.getSubReg(DestReg, SubRegIndex), in copyPhysReg()
84 RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def sube32 : SubRegIndex<32>;
30 def subo32 : SubRegIndex<32>;
31 def qhisub : SubRegIndex<64>;
32 def qsub : SubRegIndex<64>;
42 def dsub0 : SubRegIndex<64>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCQPXLoadSplat.cpp108 unsigned SubRegIndex = in runOnMachineFunction() local
110 unsigned SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex); in runOnMachineFunction()
H A DPPCRegisterInfo.td14 def sub_lt : SubRegIndex<1>;
15 def sub_gt : SubRegIndex<1, 1>;
16 def sub_eq : SubRegIndex<1, 2>;
17 def sub_un : SubRegIndex<1, 3>;
18 def sub_32 : SubRegIndex<32>;
19 def sub_64 : SubRegIndex<64>;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td32 def qqsub_0 : SubRegIndex<256>;
33 def qqsub_1 : SubRegIndex<256, 256>;
36 def qsub_0 : SubRegIndex<128>;
37 def qsub_1 : SubRegIndex<128, 128>;
41 def dsub_0 : SubRegIndex<64>;
42 def dsub_1 : SubRegIndex<64, 64>;
50 def ssub_0 : SubRegIndex<32>;
51 def ssub_1 : SubRegIndex<32, 32>;
65 def gsub_0 : SubRegIndex<32>;
66 def gsub_1 : SubRegIndex<32, 32>;
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.td14 def sub_32 : SubRegIndex<32>;
15 def sub_64 : SubRegIndex<64>;
16 def sub_lo : SubRegIndex<32>;
17 def sub_hi : SubRegIndex<32, 32>;
18 def sub_dsp16_19 : SubRegIndex<4, 16>;
19 def sub_dsp20 : SubRegIndex<1, 20>;
20 def sub_dsp21 : SubRegIndex<1, 21>;
21 def sub_dsp22 : SubRegIndex<1, 22>;
22 def sub_dsp23 : SubRegIndex<1, 23>;
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td81 def isub_lo : SubRegIndex<32>;
82 def isub_hi : SubRegIndex<32, 32>;
83 def vsub_lo : SubRegIndex<512>;
84 def vsub_hi : SubRegIndex<512, 512>;
85 def wsub_lo : SubRegIndex<1024>;
86 def wsub_hi : SubRegIndex<1024, 1024>;
87 def subreg_overflow : SubRegIndex<1, 0>;
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.td24 def subreg_l32 : SubRegIndex<32, 0>; // Also acts as subreg_ll32.
25 def subreg_h32 : SubRegIndex<32, 32>; // Also acts as subreg_lh32.
26 def subreg_l64 : SubRegIndex<64, 0>;
27 def subreg_h64 : SubRegIndex<64, 64>;
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86RegisterInfo.td24 def sub_8bit : SubRegIndex<8>;
25 def sub_8bit_hi : SubRegIndex<8, 8>;
26 def sub_8bit_hi_phony : SubRegIndex<8, 8>;
27 def sub_16bit : SubRegIndex<16>;
28 def sub_16bit_hi : SubRegIndex<16, 16>;
29 def sub_32bit : SubRegIndex<32>;
30 def sub_xmm : SubRegIndex<128>;
31 def sub_ymm : SubRegIndex<256>;
H A DX86InstrVecCompiler.td60 SubRegIndex subIdx> {
104 ValueType SrcTy, SubRegIndex SubIdx> {
178 SubRegIndex SubIdx> {
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.td15 def sub_32 : SubRegIndex<32>;
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTarget.td74 // SubRegIndex - Use instances of SubRegIndex to identify subregisters.
75 class SubRegIndex<int size, int offset = 0> {
87 // ComposedOf - A list of two SubRegIndex instances, [A, B].
90 list<SubRegIndex> ComposedOf = [];
108 list<SubRegIndex> CoveringSubRegIndices = [];
113 class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
114 : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
117 // See SubRegIndex.
149 list<SubRegIndex> SubRegIndices = [];
351 class RegisterTuples<list<SubRegIndex> Indices, list<dag> Regs> {
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/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td25 def sub_even : SubRegIndex<32>;
26 def sub_odd : SubRegIndex<32, 32>;
27 def sub_even64 : SubRegIndex<64>;
28 def sub_odd64 : SubRegIndex<64, 64>;
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td22 def sub_32 : SubRegIndex<32>;
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp514 void TargetRegisterInfo::dumpReg(unsigned Reg, unsigned SubRegIndex, in dumpReg() argument
516 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.td32 def sub_lo : SubRegIndex<8>;
33 def sub_hi : SubRegIndex<8, 8>;
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.td51 def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp1527 for (const auto &SubRegIndex : SubRegIndices) { in computeSubRegLaneMasks() local
1528 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
1530 LaneMask |= SubRegIndex.LaneMask; in computeSubRegLaneMasks()
2048 CodeGenSubRegIndex *SubRegIndex = S->first; in computeRegUnitLaneMasks() local
2050 LaneBitmask LaneMask = SubRegIndex->LaneMask; in computeRegUnitLaneMasks()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h626 static void dumpReg(unsigned Reg, unsigned SubRegIndex = 0,
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td28 def sub_32 : SubRegIndex<32>;

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