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Searched refs:SubReg (Results 1 – 25 of 56) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DLiveVariables.cpp198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
204 LastDefReg = SubReg; in FindLastPartialDef()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
340 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
371 unsigned SubReg = *SubRegs; in HandlePhysRegKill() local
453 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
460 if (Live.count(SubReg)) in HandlePhysRegDef()
462 if (PhysRegDef[SubReg] || PhysRegUse[SubReg]) { in HandlePhysRegDef()
475 unsigned SubReg = *SubRegs; in HandlePhysRegDef() local
476 if (!Live.count(SubReg)) in HandlePhysRegDef()
[all …]
H A DPeepholeOptimizer.cpp295 addSource(Reg, SubReg); in ValueTrackerResult()
330 return RegSrcs[Idx].SubReg; in getSrcSubReg()
738 if (PHICount > 0 && CurSrcPair.SubReg != 0) in findNextSource()
772 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg); in insertPHI()
1116 RegSubRegPair LookupSrc(Def.Reg, Def.SubReg); in getNewSource()
1127 LookupSrc.SubReg = Res.getSrcSubReg(0); in getNewSource()
1238 .addReg(NewSrc.Reg, 0, NewSrc.SubReg); in rewriteSource()
1240 if (Def.SubReg) { in rewriteSource()
1905 if (RegSeqInput.SubReg) in getNextSourceFromRegSequence()
1957 BaseReg.SubReg) in getNextSourceFromInsertSubreg()
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H A DDetectDeadLanes.cpp178 unsigned SubReg = MI.getOperand(2).getImm(); in isCrossCopy() local
179 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx); in isCrossCopy()
428 unsigned SubReg = MO.getSubReg(); in determineInitialUsedLanes() local
451 if (SubReg == 0) in determineInitialUsedLanes()
454 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg); in determineInitialUsedLanes()
461 unsigned SubReg = MO.getSubReg(); in isUndefRegAtInput() local
462 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in isUndefRegAtInput()
H A DLiveRangeCalc.cpp87 unsigned SubReg = MO.getSubReg(); in calculate() local
88 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
89 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
177 unsigned SubReg = MO.getSubReg(); in extendToUses() local
178 if (SubReg != 0) { in extendToUses()
179 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
H A DScheduleDAGInstrs.cpp334 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) { in addPhysRegDeps() local
335 if (Uses.contains(*SubReg)) in addPhysRegDeps()
336 Uses.eraseAll(*SubReg); in addPhysRegDeps()
338 Defs.eraseAll(*SubReg); in addPhysRegDeps()
370 unsigned SubReg = MO.getSubReg(); in getLaneMaskForMO() local
371 if (SubReg == 0) in getLaneMaskForMO()
373 return TRI->getSubRegIndexLaneMask(SubReg); in getLaneMaskForMO()
H A DMachineInstrBundle.cpp200 unsigned SubReg = *SubRegs; in finalizeBundle() local
201 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
202 LocalDefs.push_back(SubReg); in finalizeBundle()
H A DLiveIntervals.cpp557 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
558 if (SubReg != 0) { in shrinkToUses()
559 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
997 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
998 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg) in updateAllRanges()
1395 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1396 if (SubReg != 0 && LaneMask.any() in findLastUseBefore()
1397 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask).none()) in findLastUseBefore()
1502 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
1503 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
H A DTailDuplicator.cpp407 if (VI->second.SubReg != 0) { in duplicateInstruction()
409 VI->second.SubReg); in duplicateInstruction()
429 VI->second.SubReg)); in duplicateInstruction()
440 .addReg(VI->second.Reg, 0, VI->second.SubReg); in duplicateInstruction()
991 .addReg(CI.second.Reg, 0, CI.second.SubReg); in appendCopies()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64AdvSIMDScalarPass.cpp105 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
107 if (SubReg) in isGPR64()
114 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
118 SubReg == 0) || in isFPR64()
120 SubReg == AArch64::dsub); in isFPR64()
122 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
130 unsigned &SubReg) { in getSrcFromCopy() argument
131 SubReg = 0; in getSrcFromCopy()
139 SubReg = AArch64::dsub; in getSrcFromCopy()
153 SubReg = MI->getOperand(1).getSubReg(); in getSrcFromCopy()
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H A DAArch64RegisterInfo.cpp152 for (MCSubRegIterator SubReg(AArch64::GPR64commonRegClass.getRegister(i), in UpdateCustomCallPreservedMask() local
154 SubReg.isValid(); ++SubReg) { in UpdateCustomCallPreservedMask()
157 UpdatedMask[*SubReg / 32] |= 1u << (*SubReg % 32); in UpdateCustomCallPreservedMask()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCRegisterInfo.cpp44 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
45 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
50 if (*Subs == SubReg) in getSubRegIndex()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td35 class GP8<GPR SubReg, string n> : PPCReg<n> {
36 let HWEncoding = SubReg.HWEncoding;
37 let SubRegs = [SubReg];
43 let HWEncoding = SubReg.HWEncoding;
44 let SubRegs = [SubReg];
60 let HWEncoding = SubReg.HWEncoding;
61 let SubRegs = [SubReg];
73 class VR<VF SubReg, string n> : PPCReg<n> {
76 let SubRegs = [SubReg];
83 let HWEncoding = SubReg.HWEncoding;
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp294 unsigned Reg, unsigned SubReg, in instAccessReg() argument
306 LaneBitmask Overlap = TRI.getSubRegIndexLaneMask(SubReg) & in instAccessReg()
316 unsigned Reg, unsigned SubReg, in instReadsReg() argument
318 return instAccessReg(MI->uses(), Reg, SubReg, TRI); in instReadsReg()
322 unsigned Reg, unsigned SubReg, in instModifiesReg() argument
324 return instAccessReg(MI->defs(), Reg, SubReg, TRI); in instModifiesReg()
435 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
436 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
437 .addReg(Y1.Reg, 0, Y1.SubReg) in matchSwap()
438 .addReg(X1.Reg, 0, X1.SubReg).getInstr(); in matchSwap()
H A DSIAddIMGInit.cpp154 unsigned SubReg = in runOnMachineFunction() local
156 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg) in runOnMachineFunction()
161 .addReg(SubReg) in runOnMachineFunction()
H A DSIFormMemoryClauses.cpp363 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
365 if (!SubReg) in runOnMachineFunction()
367 B.addDef(R.first, S, SubReg); in runOnMachineFunction()
372 forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) { in runOnMachineFunction() argument
373 B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg); in runOnMachineFunction()
H A DSIRegisterInfo.cpp589 unsigned SubReg = NumSubRegs == 1 ? in buildSpillLoadStore() local
606 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
705 unsigned SubReg = NumSubRegs == 1 ? in spillSGPR() local
739 .addReg(SubReg, getKillRegState(IsKill)) // sdata in spillSGPR()
763 .addReg(SubReg, getKillRegState(IsKill)) in spillSGPR()
782 .addReg(SubReg, SubKillState); in spillSGPR()
877 unsigned SubReg = NumSubRegs == 1 ? in restoreSGPR() local
901 BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg) in restoreSGPR()
917 SubReg) in restoreSGPR()
1517 unsigned SubReg, in shouldCoalesce() argument
[all …]
H A DSIRegisterInfo.h211 unsigned SubReg,
232 MachineInstr *findReachingDef(unsigned Reg, unsigned SubReg,
H A DSIInstrInfo.h755 if (unsigned SubReg = MO.getSubReg()) { in getOpSize() local
758 getRegClass(MO.getReg()), SubReg)) >= 32 && in getOpSize()
760 return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4; in getOpSize()
938 if (!P.SubReg) in isOfRegClass()
941 return RC == TRI->getMatchingSuperRegClass(RC, &TRC, P.SubReg); in isOfRegClass()
953 unsigned SubReg);
H A DR600OptimizeVectorRegisters.cpp217 unsigned SubReg = (*It).first; in RebuildVector() local
224 .addReg(SubReg) in RebuildVector()
226 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h428 unsigned SubReg; member
430 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
431 : Reg(Reg), SubReg(SubReg) {} in Reg()
440 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
442 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
1701 std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg);
1708 RegInfo::isEqual(LHS.SubReg, RHS.SubReg);
H A DMachineInstrBuilder.h85 unsigned SubReg = 0) const {
95 SubReg,
104 unsigned SubReg = 0) const {
105 return addReg(RegNo, Flags | RegState::Define, SubReg);
111 unsigned SubReg = 0) const {
114 return addReg(RegNo, Flags, SubReg);
H A DTargetRegisterInfo.h977 unsigned SubReg, in shouldCoalesce() argument
1024 unsigned SubReg = 0; variable
1044 unsigned getSubReg() const { return SubReg; } in getSubReg()
1055 SubReg = *Idx++;
1056 if (!SubReg)
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp258 for (const auto &SubReg : SubRegs) { in inheritRegUnits() local
259 CodeGenRegister *SR = SubReg.second; in inheritRegUnits()
353 for (const auto &SubReg : Map) in computeSubRegs() local
354 if (Orphans.erase(SubReg.second)) in computeSubRegs()
355 SubRegs[RegBank.getCompositeSubRegIndex(Idx, SubReg.first)] = SubReg.second; in computeSubRegs()
359 for (const auto &SubReg : SubRegs) { in computeSubRegs() local
360 if (SubReg.second == this) { in computeSubRegs()
374 SubReg2Idx.insert(std::make_pair(SubReg.second, SubReg.first)).first; in computeSubRegs()
375 if (Ins->second == SubReg.first) in computeSubRegs()
478 const CodeGenRegister *SubReg; in computeSecondarySubRegs() local
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp84 unsigned Reg, SubReg; member
95 return (Reg == R.Reg) && (SubReg == R.SubReg); in operator ==()
629 if (DefR.SubReg) { in visitPHI()
1074 if (!R.SubReg) { in getCell()
1926 assert(!DefR.SubReg); in evaluate()
2194 if (!R.SubReg) { in evaluate()
2201 if (R.SubReg != Hexagon::isub_lo && R.SubReg != Hexagon::isub_hi) in evaluate()
2286 if (PR.SubReg) in evaluate()
2976 if (R1.SubReg) { in rewriteHexConstUses()
3043 if (SR.SubReg) { in rewriteHexConstUses()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp163 unsigned SubReg = MovMI->getOperand(1).getReg(); in eliminateZExtSeq() local
171 .addImm(0).addReg(SubReg).addImm(BPF::sub_32); in eliminateZExtSeq()

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