Lines Matching refs:SubReg
589 unsigned SubReg = NumSubRegs == 1 ? in buildSpillLoadStore() local
606 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
705 unsigned SubReg = NumSubRegs == 1 ? in spillSGPR() local
739 .addReg(SubReg, getKillRegState(IsKill)) // sdata in spillSGPR()
763 .addReg(SubReg, getKillRegState(IsKill)) in spillSGPR()
782 .addReg(SubReg, SubKillState); in spillSGPR()
877 unsigned SubReg = NumSubRegs == 1 ? in restoreSGPR() local
901 BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg) in restoreSGPR()
917 SubReg) in restoreSGPR()
947 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg) in restoreSGPR()
1517 unsigned SubReg, in shouldCoalesce() argument
1607 MachineInstr *SIRegisterInfo::findReachingDef(unsigned Reg, unsigned SubReg, in findReachingDef() argument
1619 LaneBitmask SubLanes = SubReg ? getSubRegIndexLaneMask(SubReg) in findReachingDef()