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Searched refs:Sub (Results 1 – 25 of 209) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Support/
H A DCommandLine.cpp131 if (SC == Sub) in addLiteralOption()
182 if (SC == Sub) in addOption()
184 addOption(O, Sub); in addOption()
204 SubCommand &Sub = *SC; in removeOption() local
206 Sub.OptionsMap.erase(Name); in removeOption()
217 for (auto Opt = Sub.SinkOpts.begin(); Opt != Sub.SinkOpts.end(); ++Opt) { in removeOption()
219 Sub.SinkOpts.erase(Opt); in removeOption()
242 return (!Sub.OptionsMap.empty() || !Sub.PositionalOpts.empty() || in hasOptions()
257 SubCommand &Sub = *SC; in updateArgStr() local
433 if (I == Sub.OptionsMap.end()) in LookupOption()
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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp183 return Reg == RR.Reg && Sub == RR.Sub; in operator ==()
187 return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); in operator <()
190 unsigned Reg, Sub; member
261 switch (Sub) { in INITIALIZE_PASS_DEPENDENCY()
290 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) in getLaneMask()
593 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); in getCondTfrOpcode()
778 if (RR.Sub == RD.Sub) in getReachingDefForPred()
780 if (RR.Sub == 0 || RD.Sub == 0) in getReachingDefForPred()
925 Op.setSubReg(RN.Sub); in renameInRange()
1012 RR.Sub = 0; in predicate()
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H A DHexagonBitSimplify.cpp411 if (RR.Sub == 0) { in getSubregMask()
423 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) in getSubregMask()
903 if (RR.Sub == 0) in getFinalVRegClass()
1562 Out.Sub = 0; in findMatch()
1713 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1845 unsigned Sub = 0; in matchHalf() local
1868 RH.Sub = Sub; in matchHalf()
1872 RH.Sub = 0; in matchHalf()
1897 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) in matchPackhl()
1899 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) in matchPackhl()
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H A DBitTracker.cpp344 unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub); in getRegBitWidth()
366 if (!RR.Sub) in getCell()
368 BitMask M = mask(RR.Reg, RR.Sub); in getCell()
382 assert(RR.Sub == 0 && "Unexpected sub-register in definition"); in putCell()
727 assert(RD.Sub == 0); in evaluate()
747 assert(RD.Sub == 0); in evaluate()
829 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) in visitPHI()
859 dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) in visitNonBranch()
877 assert(RD.Sub == 0 && "Unexpected sub-register in definition"); in visitNonBranch()
1001 BitMask OM = ME.mask(OldRR.Reg, OldRR.Sub); in subst()
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H A DHexagonBlockRanges.h35 unsigned Reg, Sub; member
38 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
H A DBitTracker.h143 : Reg(R), Sub(S) {} in Reg()
145 : Reg(MO.getReg()), Sub(MO.getSubReg()) {} in RegisterRef()
147 unsigned Reg, Sub; member
465 virtual BitMask mask(unsigned Reg, unsigned Sub) const;
H A DHexagonAsmPrinter.cpp451 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext); in HexagonProcessInstruction() local
453 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext))); in HexagonProcessInstruction()
487 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext); in HexagonProcessInstruction() local
489 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext))); in HexagonProcessInstruction()
514 const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext); in HexagonProcessInstruction() local
516 MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext))); in HexagonProcessInstruction()
H A DHexagonConstExtenders.cpp231 Register(unsigned R, unsigned S) : Reg(R), Sub(S) {} in Register()
233 : Reg(Op.getReg()), Sub(Op.getSubReg()) {} in Register()
237 Sub = Op.getSubReg(); in operator =()
254 /*EarlyClobber*/false, Sub); in operator MachineOperand()
261 bool operator==(Register R) const { return Reg == R.Reg && Sub == R.Sub; } in operator ==()
265 return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub); in operator <()
267 unsigned Reg = 0, Sub = 0; member
452 OS << printReg(P.Rs.Reg, &P.HRI, P.Rs.Sub); in operator <<()
469 OS << printReg(P.Ex.Rs.Reg, &P.HRI, P.Ex.Rs.Sub); in operator <<()
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
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/freebsd-12.1/contrib/llvm/lib/MC/MCDisassembler/
H A DMCExternalSymbolizer.cpp101 const MCExpr *Sub = nullptr; in tryAddingSymbolicOperand() local
106 Sub = MCSymbolRefExpr::create(Sym, Ctx); in tryAddingSymbolicOperand()
108 Sub = MCConstantExpr::create((int)SymbolicOp.SubtractSymbol.Value, Ctx); in tryAddingSymbolicOperand()
117 if (Sub) { in tryAddingSymbolicOperand()
120 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx); in tryAddingSymbolicOperand()
122 LHS = MCUnaryExpr::createMinus(Sub, Ctx); in tryAddingSymbolicOperand()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp183 const MCExpr *Sub = nullptr; in tryAddingSymbolicOperand() local
188 Sub = MCSymbolRefExpr::create(Sym, Ctx); in tryAddingSymbolicOperand()
190 Sub = MCConstantExpr::create(SymbolicOp.SubtractSymbol.Value, Ctx); in tryAddingSymbolicOperand()
199 if (Sub) { in tryAddingSymbolicOperand()
202 LHS = MCBinaryExpr::createSub(Add, Sub, Ctx); in tryAddingSymbolicOperand()
204 LHS = MCUnaryExpr::createMinus(Sub, Ctx); in tryAddingSymbolicOperand()
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp897 if (match(Sub, m_Neg(m_Value())) || match(Sub, m_FNeg(m_Value()))) in ShouldBreakUpSubtract()
906 Value *V0 = Sub->getOperand(0); in ShouldBreakUpSubtract()
910 Value *V1 = Sub->getOperand(1); in ShouldBreakUpSubtract()
914 Value *VB = Sub->user_back(); in ShouldBreakUpSubtract()
915 if (Sub->hasOneUse() && in ShouldBreakUpSubtract()
932 Value *NegVal = NegateValue(Sub->getOperand(1), Sub, ToRedo); in BreakUpSubtract()
933 BinaryOperator *New = CreateAdd(Sub->getOperand(0), NegVal, "", Sub, Sub); in BreakUpSubtract()
934 Sub->setOperand(0, Constant::getNullValue(Sub->getType())); // Drop use of op. in BreakUpSubtract()
935 Sub->setOperand(1, Constant::getNullValue(Sub->getType())); // Drop use of op. in BreakUpSubtract()
936 New->takeName(Sub); in BreakUpSubtract()
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H A DDivRemPairs.cpp117 Instruction *Sub = BinaryOperator::CreateSub(X, Mul); in optimizeDivRem() local
152 Sub->insertAfter(Mul); in optimizeDivRem()
156 RemInst->replaceAllUsesWith(Sub); in optimizeDivRem()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86WinAllocaExpander.cpp44 enum Lowering { TouchAndSub, Sub, Probe }; enumerator
109 return Sub; in getLowering()
167 case Sub: in computeLowerings()
230 case Sub: in lower()
H A DX86FlagsCopyLowering.cpp995 unsigned Sub; in rewriteSetCarryExtended() local
998 Sub = X86::SUB8rr; in rewriteSetCarryExtended()
1002 Sub = X86::SUB16rr; in rewriteSetCarryExtended()
1006 Sub = X86::SUB32rr; in rewriteSetCarryExtended()
1010 Sub = X86::SUB64rr; in rewriteSetCarryExtended()
1017 BuildMI(MBB, SetPos, SetLoc, TII->get(Sub), ResultReg) in rewriteSetCarryExtended()
/freebsd-12.1/contrib/llvm/lib/Transforms/Instrumentation/
H A DControlHeightReduction.cpp225 for (CHRScope *Sub : Next->Subs) in append()
226 Subs.push_back(Sub); in append()
262 CHRScope *Sub = *It; in split() local
263 assert(Sub && "null Sub"); in split()
266 TailSubs.push_back(Sub); in split()
489 for (CHRScope *Sub : Subs) { in print()
490 OS << *Sub << ", "; in print()
1008 for (CHRScope *Sub : Subscopes) { in findScopes()
1011 Result->addSub(Sub); in findScopes()
1014 Scopes.push_back(Sub); in findScopes()
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/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp304 MachineInstr *Sub = nullptr; in optimizeCompareInstr() local
332 Sub = &*I; in optimizeCompareInstr()
342 if (!MI && !Sub) in optimizeCompareInstr()
347 MI = Sub; in optimizeCompareInstr()
375 if (Sub) { in optimizeCompareInstr()
383 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
384 Sub->getOperand(2).getReg() == SrcReg) { in optimizeCompareInstr()
/freebsd-12.1/contrib/llvm/tools/clang/lib/Basic/
H A DModule.cpp308 for (submodule_iterator Sub = Current->submodule_begin(), in markUnavailable() local
310 Sub != SubEnd; ++Sub) { in markUnavailable()
311 if (needUpdate(*Sub)) in markUnavailable()
312 Stack.push_back(*Sub); in markUnavailable()
/freebsd-12.1/contrib/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp81 auto Sub = m_Sub(m_SpecificInt(Width), m_Value(R1)); in foldGuardedRotateToFunnelShift() local
85 m_c_Or(m_Shl(m_Value(L0), m_Value(L1)), m_LShr(m_Value(R0), Sub))); in foldGuardedRotateToFunnelShift()
94 m_c_Or(m_LShr(m_Value(L0), m_Value(L1)), m_Shl(m_Value(R0), Sub))); in foldGuardedRotateToFunnelShift()
H A DTruncInstCombine.cpp52 case Instruction::Sub: in getRelevantOperands()
114 case Instruction::Sub: in buildTruncExpressionDag()
345 case Instruction::Sub: in ReduceExpressionDag()
/freebsd-12.1/contrib/compiler-rt/lib/scudo/
H A Dscudo_allocator_secondary.h160 Stats->Sub(AllocatorStatAllocated, Size); in Deallocate()
161 Stats->Sub(AllocatorStatMapped, Size); in Deallocate()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMCodeGenPrepare.cpp341 if (Opc != Instruction::Add && Opc != Instruction::Sub) in isSafeOverflow()
351 bool IsDecreasing = ((Opc == Instruction::Sub) && !NegImm) || in isSafeOverflow()
433 case Instruction::Sub: in getNarrowIntrinsic()
501 if (Opc != Instruction::Add && Opc != Instruction::Sub) in PrepareConstants()
507 Value *NewVal = Opc == Instruction::Sub ? in PrepareConstants()
881 if (I->getOpcode() != Instruction::Add && I->getOpcode() != Instruction::Sub) in isLegalToPromote()
/freebsd-12.1/contrib/llvm/include/llvm/IR/
H A DOperator.h102 I->getOpcode() == Instruction::Sub || in classof()
108 CE->getOpcode() == Instruction::Sub || in classof()
410 : public ConcreteOperator<OverflowingBinaryOperator, Instruction::Sub> {
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUAtomicOptimizer.cpp133 case AtomicRMWInst::Sub: in visitAtomicRMWInst()
134 Op = Instruction::Sub; in visitAtomicRMWInst()
179 Op = Instruction::Sub; in visitIntrinsicInst()
H A DAMDGPU.td210 "Support SDWA (Sub-DWORD Addressing) extension"
216 "Support OMod with SDWA (Sub-DWORD Addressing) extension"
222 "Support scalar register with SDWA (Sub-DWORD Addressing) extension"
228 "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension"
234 "Support v_mac_f32/f16 with SDWA (Sub-DWORD Addressing) extension"
240 "Support clamp for VOPC with SDWA (Sub-DWORD Addressing) extension"
/freebsd-12.1/contrib/llvm/lib/TableGen/
H A DSetTheory.cpp54 RecSet Add, Sub; in apply() local
56 ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub, Loc); in apply()
58 if (!Sub.count(*I)) in apply()

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