Lines Matching refs:Sub
411 if (RR.Sub == 0) { in getSubregMask()
423 if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi) in getSubregMask()
903 if (RR.Sub == 0) in getFinalVRegClass()
908 auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void { in getFinalVRegClass() argument
910 assert(Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_lo) || in getFinalVRegClass()
911 Sub == HRI.getHexagonSubRegIndex(*RC, Hexagon::ps_sub_hi)); in getFinalVRegClass()
916 VerifySR(RC, RR.Sub); in getFinalVRegClass()
919 VerifySR(RC, RR.Sub); in getFinalVRegClass()
1352 .addReg(RS.Reg, 0, RS.Sub); in processBlock()
1353 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
1562 Out.Sub = 0; in findMatch()
1574 Out.Sub = Hexagon::isub_lo; in findMatch()
1576 Out.Sub = Hexagon::isub_hi; in findMatch()
1615 .addReg(MR.Reg, 0, MR.Sub); in processBlock()
1634 .addReg(ML.Reg, 0, ML.Sub) in processBlock()
1636 .addReg(MH.Reg, 0, MH.Sub) in processBlock()
1680 if (RS.Sub != 0) in propagateRegCopy()
1681 Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1692 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, SL.Reg, SL.Sub, MRI); in propagateRegCopy()
1693 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, SH.Reg, SH.Sub, MRI); in propagateRegCopy()
1703 Changed = HBS::replaceSubWithSub(RD.Reg, SubLo, RL.Reg, RL.Sub, MRI); in propagateRegCopy()
1704 Changed |= HBS::replaceSubWithSub(RD.Reg, SubHi, RH.Reg, RH.Sub, MRI); in propagateRegCopy()
1710 unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::isub_lo in propagateRegCopy() local
1713 Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI); in propagateRegCopy()
1845 unsigned Sub = 0; in matchHalf() local
1848 Sub = Hexagon::isub_lo; in matchHalf()
1852 Sub = Hexagon::isub_lo; in matchHalf()
1856 Sub = Hexagon::isub_hi; in matchHalf()
1860 Sub = Hexagon::isub_hi; in matchHalf()
1868 RH.Sub = Sub; in matchHalf()
1872 RH.Sub = 0; in matchHalf()
1897 if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low) in matchPackhl()
1899 if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low) in matchPackhl()
1934 ValOp.setSubReg(H.Sub); in genStoreUpperHalf()
2034 .addReg(Rs.Reg, 0, Rs.Sub) in genPackhl()
2035 .addReg(Rt.Reg, 0, Rt.Sub); in genPackhl()
2036 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genPackhl()
2063 .addReg(L.Reg, 0, L.Sub); in genExtractHalf()
2069 .addReg(L.Reg, 0, L.Sub) in genExtractHalf()
2075 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractHalf()
2089 if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low) in genCombineHalf()
2105 .addReg(H.Reg, 0, H.Sub) in genCombineHalf()
2106 .addReg(L.Reg, 0, L.Sub); in genCombineHalf()
2107 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genCombineHalf()
2162 .addReg(RS.Reg, 0, RS.Sub); in genExtractLow()
2167 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractLow()
2354 RR.Sub = Hexagon::isub_lo; in simplifyTstbit()
2357 RR.Sub = Hexagon::isub_hi; in simplifyTstbit()
2365 .addReg(RR.Reg, 0, RR.Sub) in simplifyTstbit()
2409 assert(RD.Sub == 0); in simplifyExtractLow()
2463 dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) in simplifyExtractLow()
2591 assert(RD.Sub == 0); in simplifyRCmp0()
2666 if (SR.Sub == 0 && InpDef->getOpcode() == Hexagon::C2_muxii) { in simplifyRCmp0()
3138 << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() in processLoop()
3139 << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" in processLoop()
3259 << printReg(G.Inp.Reg, HRI, G.Inp.Sub) in processLoop()
3260 << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; in processLoop()