| /freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 762 ARM_AM::ShiftOpc ShiftTy; member
772 ARM_AM::ShiftOpc ShiftTy; member
779 ARM_AM::ShiftOpc ShiftTy; member
3146 Op->PostIdxReg.ShiftTy = ShiftTy; in CreatePostIdxReg()
3473 if (ShiftTy == ARM_AM::rrx) { in tryParseShiftRegister()
3500 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || in tryParseShiftRegister()
3501 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { in tryParseShiftRegister()
3508 ShiftTy = ARM_AM::lsl; in tryParseShiftRegister()
8544 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
8569 ARM_AM::ShiftOpc ShiftTy; in processInstruction() local
[all …]
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 2612 EVT ShiftTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout()); in ExpandIntRes_SMULFIX() local
2640 SDValue SRLAmnt = DAG.getConstant(Scale, dl, ShiftTy); in ExpandIntRes_SMULFIX()
2641 SDValue SHLAmnt = DAG.getConstant(NVTSize - Scale, dl, ShiftTy); in ExpandIntRes_SMULFIX()
2659 SDValue SRLAmnt = DAG.getConstant(Scale - NVTSize, dl, ShiftTy); in ExpandIntRes_SMULFIX()
2660 SDValue SHLAmnt = DAG.getConstant(VTSize - Scale, dl, ShiftTy); in ExpandIntRes_SMULFIX()
2782 EVT ShiftTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in ExpandIntRes_Shift() local
2783 assert(ShiftTy.getScalarSizeInBits() >= in ExpandIntRes_Shift()
2786 if (ShiftOp.getValueType() != ShiftTy) in ExpandIntRes_Shift()
2787 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy); in ExpandIntRes_Shift()
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| H A D | TargetLowering.cpp | 2732 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
2740 ShiftTy))); in SimplifySetCC()
2749 ShiftTy))); in SimplifySetCC()
2765 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
2770 ShiftTy)); in SimplifySetCC()
2796 EVT ShiftTy = getShiftAmountTy(N0.getValueType(), DL, in SimplifySetCC() local
2800 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
5401 EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout()); in getExpandedFixedPointMultiplication() local
5402 Lo = DAG.getNode(ISD::SRL, dl, VT, Lo, DAG.getConstant(Scale, dl, ShiftTy)); in getExpandedFixedPointMultiplication()
5405 DAG.getConstant(VT.getScalarSizeInBits() - Scale, dl, ShiftTy)); in getExpandedFixedPointMultiplication()
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| H A D | SelectionDAGBuilder.cpp | 2849 EVT ShiftTy = DAG.getTargetLoweringInfo().getShiftAmountTy( in visitShift() local
2853 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { in visitShift()
2854 unsigned ShiftSize = ShiftTy.getSizeInBits(); in visitShift()
2860 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2867 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); in visitShift()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 785 EVT ShiftTy, SelectionDAG &DAG) { in genConstMult() argument
797 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
808 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
809 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
815 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); in genConstMult()
816 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); in genConstMult()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 187 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
2775 ARM_AM::ShiftOpc ShiftTy) { in SelectShift() argument
2818 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); in SelectShift()
2821 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); in SelectShift()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 36870 EVT ShiftTy = Shift.getValueType(); in foldXorTruncShiftIntoCmp() local
36871 if (ShiftTy != MVT::i16 && ShiftTy != MVT::i32 && ShiftTy != MVT::i64) in foldXorTruncShiftIntoCmp()
36876 Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1) in foldXorTruncShiftIntoCmp()
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