762     ARM_AM::ShiftOpc ShiftTy;  member
772     ARM_AM::ShiftOpc ShiftTy;  member
779     ARM_AM::ShiftOpc ShiftTy;  member
1243     return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;  in isPostIdxReg()
2064       ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));  in addRegShiftedRegOperands()
2075       ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));  in addRegShiftedImmOperands()
2698                                      PostIdxReg.ShiftTy);  in addPostIdxRegShiftedOperands()
2972     Op->RegShiftedReg.ShiftTy = ShTy;  in CreateShiftedRegister()
2985     Op->RegShiftedImm.ShiftTy = ShTy;  in CreateShiftedImmediate()
3141   CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,  in CreatePostIdxReg()  argument
3146     Op->PostIdxReg.ShiftTy = ShiftTy;  in CreatePostIdxReg()
3281     if (PostIdxReg.ShiftTy != ARM_AM::no_shift)  in print()
3282       OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "  in print()
3304        << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "  in print()
3309        << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"  in print()
3447   ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)  in tryParseShiftRegister()  local
3456   if (ShiftTy == ARM_AM::no_shift)  in tryParseShiftRegister()
3473   if (ShiftTy == ARM_AM::rrx) {  in tryParseShiftRegister()
3500           ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||  in tryParseShiftRegister()
3501           ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {  in tryParseShiftRegister()
3508         ShiftTy = ARM_AM::lsl;  in tryParseShiftRegister()
3524   if (ShiftReg && ShiftTy != ARM_AM::rrx)  in tryParseShiftRegister()
3525     Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,  in tryParseShiftRegister()
3529     Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,  in tryParseShiftRegister()
4899   ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;  in parsePostIdxReg()  local
4903     if (parseMemRegOffsetShift(ShiftTy, ShiftImm))  in parsePostIdxReg()
4910   Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,  in parsePostIdxReg()
8544     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
8547     case ARM::ASRr: ShiftTy = ARM_AM::asr; break;  in processInstruction()
8548     case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
8549     case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
8550     case ARM::RORr: ShiftTy = ARM_AM::ror; break;  in processInstruction()
8552     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);  in processInstruction()
8569     ARM_AM::ShiftOpc ShiftTy;  in processInstruction()  local
8572     case ARM::ASRi: ShiftTy = ARM_AM::asr; break;  in processInstruction()
8573     case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;  in processInstruction()
8574     case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;  in processInstruction()
8575     case ARM::RORi: ShiftTy = ARM_AM::ror; break;  in processInstruction()
8581     if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))  in processInstruction()
8583     unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);  in processInstruction()