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Searched refs:ShiftAmount (Results 1 – 24 of 24) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/RISCV/Utils/
H A DRISCVMatInt.cpp69 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52); in generateInstSeq() local
70 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount); in generateInstSeq()
74 Res.push_back(Inst(RISCV::SLLI, ShiftAmount)); in generateInstSeq()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.h49 unsigned ShiftAmount) const;
H A DMipsTargetStreamer.h140 void emitDSLL(unsigned DstReg, unsigned SrcReg, int16_t ShiftAmount,
H A DMipsSEISelDAGToDAG.cpp336 unsigned ShiftAmount = 0) const { in selectAddrFrameIndexOffset() argument
339 if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { in selectAddrFrameIndexOffset()
350 if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0) in selectAddrFrameIndexOffset()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp232 int16_t ShiftAmount, SMLoc IDLoc, in emitDSLL() argument
234 if (ShiftAmount >= 32) { in emitDSLL()
235 emitRRI(Mips::DSLL32, DstReg, SrcReg, ShiftAmount - 32, IDLoc, STI); in emitDSLL()
239 emitRRI(Mips::DSLL, DstReg, SrcReg, ShiftAmount, IDLoc, STI); in emitDSLL()
H A DMipsMCCodeEmitter.h189 template <unsigned ShiftAmount = 0>
H A DMipsMCCodeEmitter.cpp764 template <unsigned ShiftAmount>
774 OffBits >>= ShiftAmount; in getMemEncoding()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp952 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
957 if (ShiftAmount >= 8) { in LowerShifts()
977 ShiftAmount -= 8; in LowerShifts()
980 if (Opc == ISD::SRL && ShiftAmount) { in LowerShifts()
984 ShiftAmount -= 1; in LowerShifts()
987 while (ShiftAmount--) in LowerShifts()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp352 unsigned ShiftAmount; member
509 return ShiftedImm.ShiftAmount; in getShiftedImmShift()
795 unsigned Shift = ShiftedImm.ShiftAmount; in isAddSubImm()
1828 unsigned ShiftAmount = 0, in CreateReg() argument
1836 Op->Reg.ShiftExtend.Amount = ShiftAmount; in CreateReg()
1847 unsigned ShiftAmount = 0, in CreateVectorReg() argument
1897 Op->ShiftedImm.ShiftAmount = ShiftAmount; in CreateShiftedImm()
2654 int64_t ShiftAmount = Parser.getTok().getIntVal(); in tryParseImmWithOptionalShift() local
2656 if (ShiftAmount < 0) { in tryParseImmWithOptionalShift()
2663 if (ShiftAmount == 0 && Imm != 0) { in tryParseImmWithOptionalShift()
[all …]
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp931 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT); in ExpandSIGN_EXTEND_VECTOR_INREG() local
933 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount), in ExpandSIGN_EXTEND_VECTOR_INREG()
934 ShiftAmount); in ExpandSIGN_EXTEND_VECTOR_INREG()
H A DTargetLowering.cpp4102 unsigned ShiftAmount = OuterBitSize - InnerBitSize; in expandMUL_LOHI() local
4104 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) { in expandMUL_LOHI()
4110 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy); in expandMUL_LOHI()
4815 SDValue ShiftAmount = in scalarizeVectorStore() local
4818 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount); in scalarizeVectorStore()
4994 SDValue ShiftAmount = in expandUnalignedLoad() local
4997 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); in expandUnalignedLoad()
5112 SDValue ShiftAmount = in expandUnalignedStore() local
5116 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in expandUnalignedStore()
H A DLegalizeDAG.cpp1522 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit; in ExpandFCOPYSIGN() local
1528 if (ShiftAmount > 0) { in ExpandFCOPYSIGN()
1529 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
1531 } else if (ShiftAmount < 0) { in ExpandFCOPYSIGN()
1532 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, ShiftVT); in ExpandFCOPYSIGN()
H A DLegalizeIntegerTypes.cpp638 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT); in PromoteIntRes_ADDSUBSAT() local
640 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
642 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
646 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount); in PromoteIntRes_ADDSUBSAT()
H A DDAGCombiner.cpp8594 SDValue ShiftAmount = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in foldExtendedSignBitTest() local
8596 return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount); in foldExtendedSignBitTest()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DInstructionSimplify.cpp2521 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
2523 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
2527 Upper = C->ashr(ShiftAmount) + 1; in setLimitsForBinOp()
2530 Lower = C->ashr(ShiftAmount); in setLimitsForBinOp()
2542 unsigned ShiftAmount = Width - 1; in setLimitsForBinOp() local
2544 ShiftAmount = C->countTrailingZeros(); in setLimitsForBinOp()
2545 Lower = C->lshr(ShiftAmount); in setLimitsForBinOp()
2559 unsigned ShiftAmount = C->countLeadingOnes() - 1; in setLimitsForBinOp() local
2560 Lower = C->shl(ShiftAmount); in setLimitsForBinOp()
2564 unsigned ShiftAmount = C->countLeadingZeros() - 1; in setLimitsForBinOp() local
[all …]
/freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp474 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0; in foldVecTruncToExtElt() local
476 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0)) in foldVecTruncToExtElt()
487 unsigned Elt = ShiftAmount / DestWidth; in foldVecTruncToExtElt()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1836 uint64_t ShiftAmount = V.getConstantOperandVal(1); in factorOutPowerOf2() local
1837 if (ShiftAmount == Power) in factorOutPowerOf2()
1839 Ops[1] = CurDAG->getConstant(ShiftAmount - Power, in factorOutPowerOf2()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp2083 SDValue &Src, int &ShiftAmount, in isBitfieldPositioningOp() argument
2117 ShiftAmount = countTrailingZeros(NonZeroBits); in isBitfieldPositioningOp()
2118 MaskWidth = countTrailingOnes(NonZeroBits >> ShiftAmount); in isBitfieldPositioningOp()
2125 if (ShlImm - ShiftAmount != 0 && !BiggerPattern) in isBitfieldPositioningOp()
2127 Src = getLeftShift(CurDAG, Op, ShlImm - ShiftAmount); in isBitfieldPositioningOp()
H A DAArch64ISelLowering.cpp8148 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1); in shouldReduceLoadWidth() local
8150 if (ShiftAmount == Log2_32(LoadBytes)) in shouldReduceLoadWidth()
9227 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount, in findEXTRHalf() argument
9239 ShiftAmount = N->getConstantOperandVal(1); in findEXTRHalf()
9858 int64_t ShiftAmount; in tryCombineShiftImm() local
9868 ShiftAmount = SplatValue.getSExtValue(); in tryCombineShiftImm()
9870 ShiftAmount = CVN->getSExtValue(); in tryCombineShiftImm()
9901 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits) { in tryCombineShiftImm()
9904 DAG.getConstant(-ShiftAmount, dl, MVT::i32)); in tryCombineShiftImm()
9905 } else if (!IsRightShift && ShiftAmount >= 0 && ShiftAmount < ElemBits) { in tryCombineShiftImm()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp391 unsigned &ShiftAmount);
4509 const MCExpr *ShiftAmount; in parsePKHImm() local
4512 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parsePKHImm()
4516 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parsePKHImm()
4592 const MCExpr *ShiftAmount; in parseShifterImm() local
4594 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseShifterImm()
4598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseShifterImm()
4654 const MCExpr *ShiftAmount; in parseRotImm() local
4656 if (getParser().parseExpression(ShiftAmount, EndLoc)) { in parseRotImm()
4660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount); in parseRotImm()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp310 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in LowerShifts() local
333 while (ShiftAmount--) { in LowerShifts()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1291 template <unsigned Bits, unsigned ShiftAmount = 0>
1299 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff()))) in isMemWithSimmOffset()
1303 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant()); in isMemWithSimmOffset()
2749 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet)); in loadImmediate() local
2750 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff; in loadImmediate()
2752 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI); in loadImmediate()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12771 unsigned ShiftAmount = TrueConst->logBase2(); in PerformCMOVCombine() local
12772 if (ShiftAmount) in PerformCMOVCombine()
12781 if (ShiftAmount) in PerformCMOVCombine()
12783 DAG.getConstant(ShiftAmount, dl, MVT::i32)); in PerformCMOVCombine()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4219 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32); in getSegmentAperture() local
4220 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount); in getSegmentAperture()