| /freebsd-12.1/contrib/llvm/lib/MC/ |
| H A D | MCSchedule.cpp | 58 unsigned SchedClass) const { in computeInstrLatency()
72 const MCSchedClassDesc *SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
78 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in computeInstrLatency()
79 SCDesc = getSchedClassDesc(SchedClass); in computeInstrLatency()
82 if (SchedClass) in computeInstrLatency()
124 SchedClass = STI.resolveVariantSchedClass(SchedClass, &Inst, CPUID); in getReciprocalThroughput()
125 SCDesc = getSchedClassDesc(SchedClass); in getReciprocalThroughput()
128 if (SchedClass) in getReciprocalThroughput()
135 MCSchedModel::getReciprocalThroughput(unsigned SchedClass, in getReciprocalThroughput() argument
138 const InstrStage *I = IID.beginStage(SchedClass); in getReciprocalThroughput()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepTimingClasses.h | 20 inline bool is_TC3x(unsigned SchedClass) { in is_TC3x() argument
21 switch (SchedClass) { in is_TC3x()
47 inline bool is_TC2early(unsigned SchedClass) { in is_TC2early() argument
48 switch (SchedClass) { in is_TC2early()
57 inline bool is_TC4x(unsigned SchedClass) { in is_TC4x() argument
58 switch (SchedClass) { in is_TC4x()
72 inline bool is_TC2(unsigned SchedClass) { in is_TC2() argument
73 switch (SchedClass) { in is_TC2()
101 inline bool is_TC1(unsigned SchedClass) { in is_TC1() argument
102 switch (SchedClass) { in is_TC1()
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| H A D | HexagonInstrInfo.cpp | 2109 unsigned SchedClass = MI.getDesc().getSchedClass(); in isEarlySourceInstr() local
2110 return is_TC4x(SchedClass) || is_TC3x(SchedClass); in isEarlySourceInstr()
2301 unsigned SchedClass = MI.getDesc().getSchedClass(); in isLateResultInstr() local
2302 return !is_TC1(SchedClass); in isLateResultInstr()
2550 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC1() local
2551 return is_TC1(SchedClass); in isTC1()
2555 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2() local
2556 return is_TC2(SchedClass); in isTC2()
2560 unsigned SchedClass = MI.getDesc().getSchedClass(); in isTC2Early() local
2561 return is_TC2early(SchedClass); in isTC2Early()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 136 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass() local
137 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
147 SchedClass = STI->resolveSchedClass(SchedClass, MI, this); in resolveSchedClass()
148 SCDesc = SchedModel.getSchedClassDesc(SchedClass); in resolveSchedClass()
328 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput() local
329 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
341 unsigned SchedClass = TII->get(Opcode).getSchedClass(); in computeReciprocalThroughput() local
343 return MCSchedModel::getReciprocalThroughput(SchedClass, in computeReciprocalThroughput()
346 const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); in computeReciprocalThroughput()
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| H A D | MachinePipeliner.cpp | 776 unsigned SchedClass = MI.getDesc().getSchedClass(); in calcCriticalResources() local
777 for (const InstrStage *IS = InstrItins->beginStage(SchedClass), in calcCriticalResources()
778 *IE = InstrItins->endStage(SchedClass); in calcCriticalResources()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZHazardRecognizer.h | 123 if (!SU->SchedClass && SchedModel->hasInstrSchedModel()) in getSchedClass()
124 SU->SchedClass = SchedModel->resolveSchedClass(SU->getInstr()); in getSchedClass()
125 return SU->SchedClass; in getSchedClass()
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| H A D | SystemZScheduleZEC12.td | 107 // resources that it needs. These will be combined into a SchedClass.
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| H A D | SystemZScheduleZ196.td | 104 // resources that it needs. These will be combined into a SchedClass.
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| H A D | SystemZScheduleZ13.td | 123 // resources that it needs. These will be combined into a SchedClass.
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| H A D | SystemZScheduleZ14.td | 123 // resources that it needs. These will be combined into a SchedClass.
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | ScheduleDAGInstrs.h | 261 if (!SU->SchedClass && SchedModel.hasInstrSchedModel()) in getSchedClass()
262 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr()); in getSchedClass()
263 return SU->SchedClass; in getSchedClass()
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| H A D | TargetSubtargetInfo.h | 142 virtual unsigned resolveSchedClass(unsigned SchedClass, in resolveSchedClass() argument
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| H A D | ScheduleDAG.h | 257 const MCSchedClassDesc *SchedClass =
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| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 170 unsigned short SchedClass; // enum identifying instr sched class variable
577 unsigned getSchedClass() const { return SchedClass; } in getSchedClass()
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| H A D | MCSubtargetInfo.h | 164 resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, in resolveVariantSchedClass() argument
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| H A D | MCSchedule.h | 367 getReciprocalThroughput(unsigned SchedClass, const InstrItineraryData &IID);
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCInstrInfo.cpp | 404 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits() local
405 return ((II[SchedClass].FirstStage + HexagonStages)->getUnits()); in getUnits()
415 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getOtherReservedSlots() local
421 for (unsigned Stage = II[SchedClass].FirstStage + 1; in getOtherReservedSlots()
422 Stage < II[SchedClass].LastStage; ++Stage) { in getOtherReservedSlots()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | SubtargetEmitter.cpp | 1295 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables() local
1296 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") "; in EmitSchedClassTables()
1297 if (SchedClass.Name.size() < 18) in EmitSchedClassTables()
1298 OS.indent(18 - SchedClass.Name.size()); in EmitSchedClassTables()
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