| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 121 SDValue &SOffset, SDValue &Offset, SDValue &Offen,
1008 SOffset = CurDAG->getTargetConstant(0, DL, MVT::i32); in SelectMUBUF()
1071 SOffset = in SelectMUBUF()
1167 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32); in SelectMUBUFScratchOffen()
1197 std::tie(VAddr, SOffset) = foldFrameIndex(N0); in SelectMUBUFScratchOffen()
1204 std::tie(VAddr, SOffset) = foldFrameIndex(Addr); in SelectMUBUFScratchOffen()
1212 SDValue &SOffset, in SelectMUBUFScratchOffset() argument
1230 SOffset = CurDAG->getRegister(SOffsetReg, MVT::i32); in SelectMUBUFScratchOffset()
1715 SDValue SRsrc, VAddr, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP() local
1733 SDValue SRsrc, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP() local
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| H A D | GCNHazardRecognizer.cpp | 527 const MachineOperand *SOffset = in createsVALUHazard() local
532 (!SOffset || !SOffset->isReg())) in createsVALUHazard()
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| H A D | SIRegisterInfo.cpp | 540 unsigned SOffset = ScratchOffsetReg; in buildSpillLoadStore() local
555 SOffset = AMDGPU::NoRegister; in buildSpillLoadStore()
565 SOffset = RS->FindUnusedReg(&AMDGPU::SGPR_32RegClass); in buildSpillLoadStore()
567 if (SOffset == AMDGPU::NoRegister) { in buildSpillLoadStore()
575 SOffset = ScratchOffsetReg; in buildSpillLoadStore()
581 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset) in buildSpillLoadStore()
608 .addReg(SOffset, SOffsetRegState) in buildSpillLoadStore()
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| H A D | SIInstrInfo.cpp | 324 const MachineOperand *SOffset = getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandWithOffset() local
325 if (SOffset && SOffset->isReg()) in getMemOperandWithOffset()
337 if (SOffset) // soffset can be an inline immediate. in getMemOperandWithOffset()
338 Offset += SOffset->getImm(); in getMemOperandWithOffset()
4097 MachineOperand *SOffset = getNamedOperand(MI, AMDGPU::OpName::soffset); in legalizeOperands() local
4112 .add(*SOffset) in legalizeOperands()
4137 .add(*SOffset) in legalizeOperands()
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| H A D | SIISelLowering.cpp | 6321 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
6322 if (AMDGPU::splitMUBUFOffset(Imm, SOffset, ImmOffset, Subtarget, Align)) { in setBufferOffsets()
6324 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
6332 uint32_t SOffset, ImmOffset; in setBufferOffsets() local
6334 if (Offset >= 0 && AMDGPU::splitMUBUFOffset(Offset, SOffset, ImmOffset, in setBufferOffsets()
6337 Offsets[1] = DAG.getConstant(SOffset, DL, MVT::i32); in setBufferOffsets()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCCodeEmitter.cpp | 737 unsigned SOffset = 0; in getMachineOpValue() local
752 ++SOffset; in getMachineOpValue()
778 : SOffset; in getMachineOpValue()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 493 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset,
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| H A D | AMDGPUBaseInfo.cpp | 958 bool splitMUBUFOffset(uint32_t Imm, uint32_t &SOffset, uint32_t &ImmOffset, in splitMUBUFOffset() argument
993 SOffset = Overflow; in splitMUBUFOffset()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 294 SDValue SOffset = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl); in LowerCall() local
296 ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), StackPtr, SOffset); in LowerCall()
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