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Searched refs:SLT (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp356 MVT::SimpleValueType SLT = LT.second.getScalarType().SimpleTy; in getArithmeticInstrCost() local
362 if (SLT == MVT::i64) in getArithmeticInstrCost()
372 if (SLT == MVT::i64){ in getArithmeticInstrCost()
380 if (SLT == MVT::i64) { in getArithmeticInstrCost()
391 if (SLT == MVT::f64) in getArithmeticInstrCost()
394 if (SLT == MVT::f32 || SLT == MVT::f16) in getArithmeticInstrCost()
401 if (SLT == MVT::f64) { in getArithmeticInstrCost()
412 if ((SLT == MVT::f32 && !ST->hasFP32Denormals()) || in getArithmeticInstrCost()
413 (SLT == MVT::f16 && ST->has16BitInsts())) { in getArithmeticInstrCost()
418 if (SLT == MVT::f16 && ST->has16BitInsts()) { in getArithmeticInstrCost()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp278 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS); in select()
281 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS); in select()
285 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS); in select()
288 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS); in select()
H A DMipsCondMov.td198 defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>,
203 defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>,
231 defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>,
243 defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>,
250 defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>,
H A DMipsFastISel.cpp684 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
687 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
691 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg); in emitCmp()
697 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg); in emitCmp()
H A DMipsInstrInfo.td2072 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>,
2686 (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
2689 (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>, ISA_MIPS1;
3182 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
3236 defm : SetlePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
3237 defm : SetgtPats<GPR32, SLT, SLTu>, ISA_MIPS1;
3238 defm : SetgePats<GPR32, XORi, SLT, SLTu>, ISA_MIPS1;
H A DMipsScheduleP5600.td212 SEB, SEH, SLT, SLTu, SLL, SRA, SRL, XORi,
H A DMips16InstrInfo.td1211 // Format: SLT rx, ry MIPS16e
1823 // x >= k to x > (k - 1) and then use SLT
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td362 def SLT : ALU_rr<0b0000000, 0b010, "slt">;
516 def : InstAlias<"sltz $rd, $rs", (SLT GPR:$rd, GPR:$rs, X0)>;
517 def : InstAlias<"sgtz $rd, $rs", (SLT GPR:$rd, X0, GPR:$rs)>;
521 def : InstAlias<"sgt $rd, $rs, $rt", (SLT GPR:$rd, GPR:$rt, GPR:$rs), 0>;
726 def : PatGprGpr<setlt, SLT>;
740 def : Pat<(setgt GPR:$rs1, GPR:$rs2), (SLT GPR:$rs2, GPR:$rs1)>;
741 def : Pat<(setge GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs1, GPR:$rs2), 1)>;
742 def : Pat<(setle GPR:$rs1, GPR:$rs2), (XORI (SLT GPR:$rs2, GPR:$rs1), 1)>;
/freebsd-12.1/contrib/gdb/gdb/
H A Dhpread.c80 #define SLT(o) (HPUX_SYMFILE_INFO(o)->slt) macro
1723 SLT (objfile) = in hpread_symfile_init()
1727 bfd_get_section_contents (objfile->obfd, slt_section, SLT (objfile), in hpread_symfile_init()
2317 return (union sltentry *) &(SLT (objfile)[index * sizeof (union sltentry)]); in hpread_get_slt()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3906 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum, in expandCondBranches()
4342 FinalOpcode = Mips::SLT; in expandAliasImmediate()