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Searched refs:ResultVT (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DValueTypes.cpp37 EVT ResultVT; in getExtendedVectorVT() local
38 ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(Context), NumElements); in getExtendedVectorVT()
39 assert(ResultVT.isExtended() && "Type is not extended!"); in getExtendedVectorVT()
40 return ResultVT; in getExtendedVectorVT()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeTypes.cpp240 EVT ResultVT = N->getValueType(i); in run() local
241 LLVM_DEBUG(dbgs() << "Analyzing result type: " << ResultVT.getEVTString() in run()
243 switch (getTypeAction(ResultVT)) { in run()
265 assert(isLegalInHWReg(ResultVT) && in run()
H A DSelectionDAGBuilder.cpp7900 EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), ResultTypes[i]); in visitInlineAsm() local
7913 if (ResultVT != Val.getValueType() && in visitInlineAsm()
7914 ResultVT.getSizeInBits() == Val.getValueSizeInBits()) in visitInlineAsm()
7915 Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, Val); in visitInlineAsm()
7916 else if (ResultVT != Val.getValueType() && ResultVT.isInteger() && in visitInlineAsm()
7921 Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, Val); in visitInlineAsm()
7924 assert(ResultVT == Val.getValueType() && "Asm result value mismatch!"); in visitInlineAsm()
7925 ResultVTs[i] = ResultVT; in visitInlineAsm()
H A DDAGCombiner.cpp15588 EVT ResultVT = EVE->getValueType(0); in scalarizeExtractedVectorLoad() local
15597 ISD::LoadExtType ExtTy = ResultVT.bitsGT(VecEltVT) ? in scalarizeExtractedVectorLoad()
15631 if (ResultVT.bitsGT(VecEltVT)) { in scalarizeExtractedVectorLoad()
15634 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, in scalarizeExtractedVectorLoad()
15638 Load = DAG.getExtLoad(ExtType, SDLoc(EVE), ResultVT, in scalarizeExtractedVectorLoad()
15648 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
15649 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(EVE), ResultVT, Load); in scalarizeExtractedVectorLoad()
15651 Load = DAG.getBitcast(ResultVT, Load); in scalarizeExtractedVectorLoad()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp4389 EVT ResultVT = Op.getValueType(); in lowerEXTRACT_VECTOR_ELT() local
4418 if (ResultVT == MVT::f16) { in lowerEXTRACT_VECTOR_ELT()
4420 return DAG.getNode(ISD::BITCAST, SL, ResultVT, Result); in lowerEXTRACT_VECTOR_ELT()
4423 return DAG.getAnyExtOrTrunc(Elt, SL, ResultVT); in lowerEXTRACT_VECTOR_ELT()
9130 MVT ResultVT = NewChannels == 1 ? in adjustWritemask() local
9134 DAG.getVTList(ResultVT, MVT::Other) : DAG.getVTList(ResultVT); in adjustWritemask()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp228 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp5322 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, in extractSubVector() local
5335 return DAG.getBuildVector(ResultVT, dl, in extractSubVector()
5339 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx); in extractSubVector()
5372 EVT ResultVT = Result.getValueType(); in insertSubVector() local
5383 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx); in insertSubVector()