| /freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyMachineFunctionInfo.cpp | 40 MVT RegisterVT = TLI.getRegisterType(F.getContext(), VT); in ComputeLegalValueVTs() local
42 ValueVTs.push_back(RegisterVT); in ComputeLegalValueVTs()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 70 MVT RegisterVT = TLI.getRegisterTypeForCallingConv( in handle() local
73 VRegs.push_back(MRI.createGenericVirtualRegister(LLT{RegisterVT})); in handle()
301 static CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT, in determineLocInfo() argument
305 if (VT.getSizeInBits() >= RegisterVT.getSizeInBits()) in determineLocInfo()
550 MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(), in subTargetRegTypeForCallingConv() local
563 ISDArgs.emplace_back(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo], in subTargetRegTypeForCallingConv()
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| H A D | MipsISelLowering.h | 303 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | MipsISelLowering.cpp | 140 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
142 RegisterVT = getRegisterTypeForCallingConv(Context, CC, VT); in getVectorTypeBreakdownForCallingConv()
143 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
144 NumIntermediates = VT.getSizeInBits() < RegisterVT.getSizeInBits() in getVectorTypeBreakdownForCallingConv()
146 : VT.getSizeInBits() / RegisterVT.getSizeInBits(); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 869 MVT &RegisterVT, in getVectorTypeBreakdownMVT() argument
905 RegisterVT = DestVT; in getVectorTypeBreakdownMVT()
1221 MVT RegisterVT; in computeRegisterProperties() local
1224 NumIntermediates, RegisterVT, this); in computeRegisterProperties()
1225 RegisterTypeForVT[i] = RegisterVT; in computeRegisterProperties()
1285 MVT &RegisterVT) const { in getVectorTypeBreakdown()
1298 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown()
1332 RegisterVT = DestVT; in getVectorTypeBreakdown()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 361 MVT RegisterVT; in getCopyFromPartsVector() local
368 NumIntermediates, RegisterVT); in getCopyFromPartsVector()
378 assert(RegisterVT.getSizeInBits() == in getCopyFromPartsVector()
694 MVT RegisterVT; in getCopyToPartsVector() local
700 NumIntermediates, RegisterVT); in getCopyToPartsVector()
776 MVT RegisterVT = in RegsForValue() local
782 RegVTs.push_back(RegisterVT); in RegsForValue()
826 !RegisterVT.isInteger()) in getCopyFromRegs()
975 MVT RegisterVT = RegVTs[Value]; in AddInlineAsmOperands() local
8446 RetTys.append(NumRegs, RegisterVT); in LowerCallTo()
[all …]
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| H A D | FunctionLoweringInfo.cpp | 376 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs() local
380 unsigned R = CreateReg(RegisterVT); in CreateRegs()
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| H A D | FastISel.cpp | 1155 MVT RegisterVT = TLI.getRegisterType(CLI.RetTy->getContext(), VT); in lowerCallTo() local
1159 MyFlags.VT = RegisterVT; in lowerCallTo()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 730 MVT &RegisterVT) const;
737 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv() argument
739 RegisterVT); in getVectorTypeBreakdownForCallingConv()
1187 MVT RegisterVT; in getRegisterType() local
1190 NumIntermediates, RegisterVT); in getRegisterType()
1191 return RegisterVT; in getRegisterType()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 963 MVT RegisterVT = getRegisterTypeForCallingConv(Ctx, CC, ArgVT); in analyzeFormalArgumentsCompute() local
971 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
975 } else if (ArgVT.isVector() && RegisterVT.isVector() && in analyzeFormalArgumentsCompute()
976 ArgVT.getScalarType() == RegisterVT.getScalarType()) { in analyzeFormalArgumentsCompute()
981 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
989 MemVT = RegisterVT; in analyzeFormalArgumentsCompute()
993 if (RegisterVT.isInteger()) { in analyzeFormalArgumentsCompute()
995 } else if (RegisterVT.isVector()) { in analyzeFormalArgumentsCompute()
996 assert(!RegisterVT.getScalarType().isFloatingPoint()); in analyzeFormalArgumentsCompute()
997 unsigned NumElements = RegisterVT.getVectorNumElements(); in analyzeFormalArgumentsCompute()
[all …]
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| H A D | SIISelLowering.h | 38 unsigned &NumIntermediates, MVT &RegisterVT) const override;
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| H A D | SIISelLowering.cpp | 783 unsigned &NumIntermediates, MVT &RegisterVT) const { in getVectorTypeBreakdownForCallingConv()
789 RegisterVT = ScalarVT.getSimpleVT(); in getVectorTypeBreakdownForCallingConv()
790 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
796 RegisterVT = MVT::i32; in getVectorTypeBreakdownForCallingConv()
797 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
806 RegisterVT = VT.isInteger() ? MVT::v2i16 : MVT::v2f16; in getVectorTypeBreakdownForCallingConv()
807 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
814 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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