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Searched refs:RegClass (Results 1 – 25 of 50) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp35 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
36 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) { in constrainRegToClass()
37 unsigned NewReg = MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
57 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
66 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
67 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
69 if (!RegClass) { in constrainOperandRegClass()
85 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); in constrainOperandRegClass()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
67 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
172 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
233 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
H A DRDFRegisters.h137 const TargetRegisterClass *RegClass = nullptr; member
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td554 RegisterClass RegClass = regclass;
644 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
654 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
661 [(set typeinfo.RegClass:$dst, EFLAGS,
662 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
669 [(set typeinfo.RegClass:$dst, EFLAGS,
670 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
677 (outs typeinfo.RegClass:$dst),
678 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
694 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
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H A DX86FrameLowering.cpp587 const TargetRegisterClass *RegClass = &X86::GR64RegClass; in emitStackProbeInline() local
589 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
591 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
593 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
595 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
597 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
601 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
603 : MRI.createVirtualRegister(RegClass), in emitStackProbeInline()
605 : MRI.createVirtualRegister(RegClass); in emitStackProbeInline()
2691 auto &RegClass = in adjustStackWithPops() local
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H A DX86MCInstLower.cpp1599 if (Info.RegClass == X86::VR128RegClassID || in getRegisterWidth()
1600 Info.RegClass == X86::VR128XRegClassID) in getRegisterWidth()
1602 if (Info.RegClass == X86::VR256RegClassID || in getRegisterWidth()
1603 Info.RegClass == X86::VR256XRegClassID) in getRegisterWidth()
1605 if (Info.RegClass == X86::VR512RegClassID) in getRegisterWidth()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/InstPrinter/
H A DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in ConvertImplicitDefToConstZero() local
107 if (RegClass == &WebAssembly::I32RegClass) { in ConvertImplicitDefToConstZero()
110 } else if (RegClass == &WebAssembly::I64RegClass) { in ConvertImplicitDefToConstZero()
113 } else if (RegClass == &WebAssembly::F32RegClass) { in ConvertImplicitDefToConstZero()
118 } else if (RegClass == &WebAssembly::F64RegClass) { in ConvertImplicitDefToConstZero()
123 } else if (RegClass == &WebAssembly::V128RegClass) { in ConvertImplicitDefToConstZero()
598 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
599 unsigned TeeReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
600 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
603 TII->get(GetTeeOpcode(RegClass)), TeeReg) in MoveAndTeeForMultiUse()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h48 std::unique_ptr<RCInfo[]> RegClass; variable
75 const RCInfo &RCI = RegClass[RC->getID()]; in get()
H A DRegisterScavenging.h163 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
164 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
93 RCInfo &RCI = RegClass[RC->getID()]; in compute()
H A DMachineRegisterInfo.cpp159 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass, in createVirtualRegister() argument
161 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
162 assert(RegClass->isAllocatable() && in createVirtualRegister()
167 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
H A DTargetInstrInfo.cpp51 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
53 return TRI->getPointerRegClass(MF, RegClass); in getRegClass()
56 if (RegClass < 0) in getRegClass()
60 return TRI->getRegClass(RegClass); in getRegClass()
H A DRenameIndependentSubregs.cpp134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
142 unsigned NewVReg = MRI->createVirtualRegister(RegClass); in INITIALIZE_PASS_DEPENDENCY()
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DRISCVCompressInstEmitter.cpp112 bool validateRegister(Record *Reg, Record *RegClass);
132 bool RISCVCompressInstEmitter::validateRegister(Record *Reg, Record *RegClass) { in validateRegister() argument
134 assert(RegClass->isSubClassOf("RegisterClass") && "RegClass record should be" in validateRegister()
136 CodeGenRegisterClass RC = Target.getRegisterClass(RegClass); in validateRegister()
H A DCodeGenRegisters.cpp1525 for (auto &RegClass : RegClasses) { in computeSubRegLaneMasks() local
1528 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr) in computeSubRegLaneMasks()
1538 RegClass.LaneMask = LaneMask; in computeSubRegLaneMasks()
1586 for (auto &RegClass : RegBank.getRegClasses()) { in computeUberSets() local
1587 if (!RegClass.Allocatable) in computeUberSets()
1590 const CodeGenRegister::Vec &Regs = RegClass.getMembers(); in computeUberSets()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DUtils.h48 const TargetRegisterClass &RegClass);
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUMachineCFGStructurizer.cpp1933 unsigned TrueBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1934 unsigned FalseBBReg = MRI->createVirtualRegister(RegClass); in rewriteCodeBBTerminator()
1999 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2000 unsigned NextDestReg = MRI->createVirtualRegister(RegClass); in insertChainedPHI()
2059 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2060 unsigned PHIDestReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2061 unsigned IfSourceReg = MRI->createVirtualRegister(RegClass); in rewriteLiveOutRegs()
2174 const TargetRegisterClass *RegClass = in createEntryPHI() local
2313 unsigned CodeBBSelectReg = MRI->createVirtualRegister(RegClass); in createIfRegion()
2449 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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H A DSIInstrInfo.cpp637 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
638 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
646 if (RegClass == &AMDGPU::SReg_64RegClass || in materializeImmediate()
647 RegClass == &AMDGPU::SGPR_64RegClass || in materializeImmediate()
654 if (RegClass == &AMDGPU::VGPR_32RegClass) { in materializeImmediate()
667 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
2555 if (OpInfo.RegClass < 0) in isImmOperandLegal()
2840 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
2882 if (RegClass != -1) { in verifyInstruction()
3265 Desc.OpInfo[OpNo].RegClass == -1) { in getOpRegClass()
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H A DGCNHazardRecognizer.cpp518 VDataRCID = Desc.OpInfo[VDataIdx].RegClass; in createsVALUHazard()
543 AMDGPU::getRegBitWidth(Desc.OpInfo[SRsrcIdx].RegClass) == 256); in createsVALUHazard()
549 if (AMDGPU::getRegBitWidth(Desc.OpInfo[DataIdx].RegClass) > 64) in createsVALUHazard()
H A DAMDGPUISelDAGToDAG.cpp324 int RegClass = Desc.OpInfo[OpIdx].RegClass; in getOperandRegClass() local
325 if (RegClass == -1) in getOperandRegClass()
328 return Subtarget->getRegisterInfo()->getRegClass(RegClass); in getOperandRegClass()
418 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector() local
422 RegClass); in SelectBuildVector()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp97 #define DECODE_OPERAND_REG(RegClass) \ argument
98 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
344 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h73 int16_t RegClass;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1512 SDValue RegClass = in createGPRPairNode() local
1516 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
1523 SDValue RegClass = in createSRegPairNode() local
1527 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createSRegPairNode()
1534 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1538 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createDRegPairNode()
1549 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createQRegPairNode()
1557 SDValue RegClass = in createQuadSRegsNode() local
1563 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadSRegsNode()
1578 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1, in createQuadDRegsNode()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.td818 class PPRAsmOperand <string name, string RegClass, int Width>: AsmOperandClass {
821 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
1102 class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandCl…
1104 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
1110 …4ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{

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