Lines Matching refs:RegClass
636 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg); in materializeImmediate() local
637 if (RegClass == &AMDGPU::SReg_32RegClass || in materializeImmediate()
638 RegClass == &AMDGPU::SGPR_32RegClass || in materializeImmediate()
639 RegClass == &AMDGPU::SReg_32_XM0RegClass || in materializeImmediate()
640 RegClass == &AMDGPU::SReg_32_XM0_XEXECRegClass) { in materializeImmediate()
646 if (RegClass == &AMDGPU::SReg_64RegClass || in materializeImmediate()
647 RegClass == &AMDGPU::SGPR_64RegClass || in materializeImmediate()
648 RegClass == &AMDGPU::SReg_64_XEXECRegClass) { in materializeImmediate()
654 if (RegClass == &AMDGPU::VGPR_32RegClass) { in materializeImmediate()
659 if (RegClass == &AMDGPU::VReg_64RegClass) { in materializeImmediate()
667 if (RI.isSGPRClass(RegClass)) { in materializeImmediate()
668 if (RI.getRegSizeInBits(*RegClass) > 32) { in materializeImmediate()
677 ArrayRef<int16_t> SubIndices = RI.getRegSplitParts(RegClass, EltSize); in materializeImmediate()
2555 if (OpInfo.RegClass < 0) in isImmOperandLegal()
2840 int RegClass = Desc.OpInfo[i].RegClass; in verifyInstruction() local
2882 if (RegClass != -1) { in verifyInstruction()
2888 const TargetRegisterClass *RC = RI.getRegClass(RegClass); in verifyInstruction()
3265 Desc.OpInfo[OpNo].RegClass == -1) { in getOpRegClass()
3273 unsigned RCID = Desc.OpInfo[OpNo].RegClass; in getOpRegClass()
3294 unsigned RCID = get(MI.getOpcode()).OpInfo[OpIdx].RegClass; in legalizeOpWithMove()
3400 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC; in isLegalRegOperand()
3420 OpInfo.RegClass != -1 ? RI.getRegClass(OpInfo.RegClass) : nullptr; in isOperandLegal()
4030 unsigned RsrcRC = get(MI.getOpcode()).OpInfo[RsrcIdx].RegClass; in legalizeOperands()
5105 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass); in findUsedSGPR()
5503 const auto RCID = MI.getDesc().OpInfo[Idx].RegClass; in isBufferSMRD()