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Searched refs:Rd (Results 1 – 25 of 46) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstrThumb2.td301 bits<4> Rd;
314 bits<4> Rd;
340 bits<4> Rd;
353 bits<4> Rd;
379 bits<4> Rd;
389 bits<4> Rd;
410 bits<4> Rd;
424 bits<4> Rd;
438 bits<4> Rd;
451 bits<4> Rd;
[all …]
H A DARMInstrInfo.td1667 bits<4> Rd;
1693 bits<4> Rd;
2051 bits<4> Rd;
2270 bits<4> Rd;
3387 bits<4> Rd;
3401 bits<4> Rd;
3415 bits<4> Rd;
3431 bits<4> Rd;
3445 bits<4> Rd;
3933 "bfc", "\t$Rd, $imm", "$src = $Rd",
[all …]
H A DARMInstrThumb.td869 bits<3> Rd;
871 let Inst{2-0} = Rd;
879 bits<3> Rd;
890 bits<3> Rd;
899 bits<3> Rd;
1163 bits<3> Rd;
1181 bits<4> Rd;
1191 bits<3> Rd;
1203 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1206 bits<3> Rd;
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td1606 bits<5> Rd;
1641 bits<5> Rd;
1652 bits<5> Rd;
1666 bits<5> Rd;
1710 bits<5> Rd;
1765 bits<5> Rd;
1832 bits<5> Rd;
1990 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
2189 // add Rd, Rb, -imm -> sub Rd, Rn, imm
6491 "\t$Rd, $Rn", "$Rd = $dst", pat>,
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H A DAArch64PBQPRegAlloc.cpp161 if (Rd == Ra) in addIntraChainConstraint()
187 const LiveInterval &ld = LIs.getInterval(Rd); in addIntraChainConstraint()
249 if (Rd != Ra) { in addInterChainConstraint()
253 Chains.insert(Rd); in addInterChainConstraint()
258 Chains.insert(Rd); in addInterChainConstraint()
263 const LiveInterval &ld = LIs.getInterval(Rd); in addInterChainConstraint()
266 if (r == Rd) in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
366 if (addIntraChainConstraint(G, Rd, Ra)) in apply()
367 addInterChainConstraint(G, Rd, Ra); in apply()
[all …]
H A DAArch64PBQPRegAlloc.h33 bool addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
36 void addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, unsigned Ra);
H A DAArch64InstrInfo.td804 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
809 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
817 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
820 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
1366 def : InstAlias<"rev64 $Rd, $Rn", (REVXr GPR64:$Rd, GPR64:$Rn), 0>;
3074 def FMOVH0 : Pseudo<(outs FPR16:$Rd), (ins), [(set f16:$Rd, (fpimm0))]>,
3076 def FMOVS0 : Pseudo<(outs FPR32:$Rd), (ins), [(set f32:$Rd, (fpimm0))]>,
3078 def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
3082 def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
3084 def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;
[all …]
H A DAArch64SchedPredicates.td276 [// MOV {Rd, SP}, {SP, Rn} =>
277 // ADD {Rd, SP}, {SP, Rn}, #0
290 // MOV Rd, Rm =>
291 // ORR Rd, ZR, Rm, LSL #0
359 [// ORR Rd, ZR, #0
H A DAArch64InstrAtomics.td381 let Constraints = "@earlyclobber $Rd,@earlyclobber $scratch",
383 def CMP_SWAP_8 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
387 def CMP_SWAP_16 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
391 def CMP_SWAP_32 : Pseudo<(outs GPR32:$Rd, GPR32:$scratch),
395 def CMP_SWAP_64 : Pseudo<(outs GPR64:$Rd, GPR32:$scratch),
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td37 // Rd - 64-bit registers.
38 class Rd<bits<5> num, string n, list<Register> subregs,
99 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>;
100 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>;
101 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>;
102 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>;
103 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>;
104 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>;
105 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>;
106 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>;
[all …]
H A DHexagonPseudo.td66 def CONST32 : CONSTLDInst<(outs IntRegs:$Rd), (ins i32imm:$v),
67 "$Rd = CONST32(#$v)", []>;
68 def CONST64 : CONSTLDInst<(outs DoubleRegs:$Rd), (ins i64imm:$v),
69 "$Rd = CONST64(#$v)", []>;
261 def PS_fi : Pseudo<(outs IntRegs:$Rd),
264 def PS_fia : Pseudo<(outs IntRegs:$Rd),
314 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
333 def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
494 def PS_vmulw : PseudoM<(outs DoubleRegs:$Rd),
498 def PS_vmulw_acc : PseudoM<(outs DoubleRegs:$Rd),
[all …]
H A DHexagonConstExtenders.cpp324 Register Rd; member
497 if (ED.Rd.Reg != 0) in operator <<()
498 OS << printReg(ED.Rd.Reg, &HRI, ED.Rd.Sub); in operator <<()
1133 if (Rd != Register(Op)) in getOffsetRange()
1162 ED.Rd = MI.getOperand(OpNum-1); in recordExtender()
1182 ED.Rd = MI.getOperand(0); in recordExtender()
1195 ED.Rd = MI.getOperand(0); in recordExtender()
1204 ED.Rd = MI.getOperand(0); in recordExtender()
1278 assert(ED.Rd.Reg != 0); in assignInits()
1885 assert(ED.Rd.Sub == 0 && ExtR.Sub == 0); in replaceInstr()
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H A DHexagonIntrinsicsV5.td303 // Rd=[cround|round](Rs,Rt)[:sat]
304 // Rd=[cround|round](Rs,#u5)[:sat]
337 // Rd=vaddhub(Rss,Rtt):sat
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td410 "mov\t$imm16, $Rd",
544 "ld\t$src, $Rd",
584 "mov\t$imm, $Rd",
643 "st\t$Rd, $dst",
694 let Rd = R2.Num;
737 let Rd = PC.Num;
779 [(set (i32 GPR:$Rd),
793 let Rd = PC.Num;
800 let Rd = PC.Num;
815 "popc\t$Rs1, $Rd",
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H A DLanaiInstrFormats.td91 bits<5> Rd;
99 let Inst{27 - 23} = Rd;
151 bits<5> Rd;
159 let Inst{27 - 23} = Rd;
199 bits<5> Rd;
210 let Inst{27 - 23} = Rd;
260 bits<5> Rd;
429 bits<5> Rd;
457 bits<5> Rd;
502 bits<5> Rd;
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/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td368 // ADDW Rd+1:Rd, Rr+1:Rr
391 // ADCW Rd+1:Rd, Rr+1:Rr
451 // SUBIW Rd+1:Rd, K+1:K
668 // ANDI Rd+1:Rd, K+1:K
686 // ORIW Rd+1:Rd, K+1,K
711 // COMW Rd+1:Rd
1151 // LDW Rd+1:Rd, P
1177 // LDW Rd+1:Rd, P+
1195 // LDW Rd+1:Rd, -P
1219 // LDDW Rd+1:Rd, P+q
[all …]
H A DAVRDevices.td32 // `LDS Rd, K`
55 // The device supports `ADDI Rd, K`, `SUBI Rd, K`.
74 // The device supports the `LPM Rd, Z[+] instruction.
76 "The device supports the `LPM Rd, Z[+]` "
83 // The device supports the `ELPM Rd, Z[+]` instructions.
85 "The device supports the `ELPM Rd, Z[+]` "
/freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1184 Rd = 7; in EmulateADDRdSPImm()
1244 Rd = 7; in EmulateMOVRdSP()
1247 Rd = 12; in EmulateMOVRdSP()
1349 if (Rd == 13) in EmulateMOVRdRm()
2408 uint32_t Rd; in EmulateSUBSPImm() local
2413 Rd = 13; in EmulateSUBSPImm()
3865 Rn = Rd; in EmulateShiftReg()
5980 uint32_t Rd; in EmulateADR() local
6064 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) in EmulateANDImm()
8871 if (Rd == 13 || (Rd == 15 && !setflags) || BadReg(Rn)) in EmulateEORImm()
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H A DEmulateInstructionARM.h201 const uint32_t Rd, bool setflags,
206 const uint32_t Rd) { in WriteCoreReg() argument
208 return WriteCoreRegOptionalFlags(context, result, Rd, false); in WriteCoreReg()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2333 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLDInstruction()
2660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVSTInstruction()
2930 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD1DupInstruction()
2977 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD2DupInstruction()
3025 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD3DupInstruction()
3060 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVLD4DupInstruction()
3113 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeNEONModImmInstruction()
3158 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeVSHLMaxInstruction()
3201 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; in DecodeTBLInstruction()
4255 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) in DecodeDoubleRegStore()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td196 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[72]>;
197 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[73]>;
198 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[74]>;
199 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[75]>;
200 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[76]>;
201 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[77]>;
202 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[78]>;
203 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[79]>;
204 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[80]>;
205 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[81]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp843 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
934 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
996 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1505 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1562 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1593 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1632 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1649 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1668 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
1683 if (Rd == 31 && !S) in DecodeAddSubImmShift()
[all …]
/freebsd-12.1/contrib/compiler-rt/lib/xray/
H A Dxray_mips.cc48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
H A Dxray_mips64.cc49 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction() argument
51 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode); in encodeSpecialInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp198 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local
200 switch (Rd) { in DecodeDstAddrMode()

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